DM74ALS174 • DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
September 1986
Revised February 2000
DM74ALS174 • DM74ALS175
Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. Both have an asynchro-
nous clear input, and the quad (DM74ALS175) version fea-
tures complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s
Advanced oxide-isolated ion-implanted Schottky TTL
process
s
Pin and functional compatible with LS family counterpart
s
Typical clock frequency maximum is 80 MHz
s
Switching performance guaranteed over full temperature
and V
CC
supply range
Ordering Code:
Ordering Code
DM74ALS174M
DM74ALS174SJ
DM74ALS174N
DM74ALS175M
DM74ALS175SJ
DM74ALS175N
Package Number
M16A
M16D
N16E
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74ALS174
DM74ALS175
© 2000 Fairchild Semiconductor Corporation
DS006112
www.fairchildsemi.com
DM74ALS174 • DM74ALS175
Absolute Maximum Ratings
(Note 2)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Typical
θ
JA
N Package
M Package
77.9°C/W
107.3°C/W
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 2:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
V
CC
V
IH
V
IL
I
OH
I
OL
t
W
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Pulse Width
Clock
HIGH or LOW
Clear LOW
4.5
2
5
5.5
0.8
−0.4
8
V
V
V
mA
mA
ns
10
10
10↑
6↑
0↑
0
0
50
70
t
SETUP
Setup Time (Note 3)
Data Input
Clear
Inactive State
ns
ns
MHz
°C
t
HOLD
f
CLOCK
T
A
Data Hold Time (Note 3)
Clock Frequency
Free Air Operating Temperature
Note 3:
The symbol
↑
indicates that the rising edge of the clock is used as reference.
3
www.fairchildsemi.com
DM74ALS174 • DM74ALS175
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25°C.
Symbol
V
IK
V
OH
V
OL
I
I
I
IH
I
IL
I
O
I
CC
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
Input Current at
Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Output Drive Current
Supply Current
I
OH
= −400 µA
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V
V
CC
=
5.5V, V
IN
=
7V
V
CC
=
5.5V, V
IH
=
2.7V
V
CC
=
5.5V, V
IN
=
0.4V
V
CC
=
5.5V, V
O
=
2.25V
V
CC
=
5.5V
Clock
=
4.5V
Clear
=
GND
D Input
=
GND
DM74ALS174
DM74ALS175
−30
11
8
I
OL
=
8 mA
Conditions
V
CC
=
4.5V, I
IN
= −18
mA
V
CC
−
2
V
CC
−
1.6
0.35
0.5
0.1
20
−0.1
−112
19
mA
14
Min
Typ
Max
−1.5
Units
V
V
V
mA
µA
mA
mA
Switching Characteristics
over recommended operating free air temperature range
Symbol
f
MAX
t
PLH
Parameter
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level
Output From Clear (175 Only)
t
PHL
Propagation Delay Time
HIGH-to-LOW Level
Output From Clear
t
PLH
Propagation Delay Time
LOW-to-HIGH Level
Output From Clock
t
PHL
Propagation Delay Time
HIGH-to-LOW Level
Output From Clock
5
17
ns
3
15
ns
8
23
ns
R
L
=
500Ω
C
L
=
50 pF
V
CC
=
4.5V to 5.5V
5
18
ns
Conditions
Min
50
Max
Units
MHz
www.fairchildsemi.com
4
京公网安备 11010802033920号
EEWORLD
