Features
•
Smart Card Interface
– Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards
Card Clock Stop High or Low for Card Power-down Modes
Support Synchronous Cards with C4 and C8 Contacts
Card Detection and Automatic de-activation Sequence
Programmable Activation Sequence
– Direct Connection to the Smart Card
Logic Level Shifters
Short Circuit Current Limitation
8kV+ ESD Protection (MIL/STD 883 Class 3)
– Programmable Voltage
5V ±5% at 65 mA (Class A)
3V ±0.2V at 65 mA (Class B)
1.8V ±0.14V at 40 mA
– Low Ripple Noise: < 200 mV Max
Versatile Host Interface
– ICAM (Conditional Access) Compatible
– Two Wire Interface (TWI) Link
Programmable Address Allow up to 8 Devices
– Programmable Interrupt Output
– Automatic Level Shifter (1.6V to V
CC
)
Reset Output Includes
– Power-On Reset (POR)
– Power-Fail Detector (PFD)
High-efficiency Step-up Converter: 80 to 98% Efficiency
Extended Voltage Operation: 2.85 to 5.5V
Low Power Consumption
– 1 mA Maximum Operating Current
– 150 mA Maximum In-rush Current
– 20
µA
Typical Power-down Current (without Smart Card)
4 to 48 MHz Clock Input (7 MHz Min for Step-up Converter)
Industrial Temperature Range: -40 to +85°C
Packages: SO28 and QFN28
•
Smart Card
Reader
Interface with
Power
Management
AT83C24
•
•
•
•
•
•
•
Description
The AT83C24 is a smart card reader interface IC for smart card reader/writer applica-
tions such as EFT/POS terminals and set top boxes. It enables the management of
any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in
parallel using the programmable TWI address.
Its high efficiency DC/DC converter, low quiescent current in standby mode makes it
particularly suited to low power and portable applications. The reduced bill of material
allows reducing significantly the system cost. A sophisticated protection system guar-
antees timely and controlled shutdown upon error conditions.
4234C–SCR–04/04
1
Acronyms
TWI: Two-wire Interface
POR: Power On Reset
PFD: Power Fail Detect
ART: Automatic Reset Transition
ATR: Answer To Reset
Block Diagram
V
CC
VSS
LI
CVSS
DVCC
EVCC
RESET
Voltage
supervisor
POR/PFD
CVCC
DC/DC
Converter
PRES/ INT
A2, A1, A0, CMDVCC
SCL
SDA
TWI
Controller
Main
Control
& Logic Unit
Timer
16 Bits
Clocks Controller
CLK
Analog
Drivers
CPRES
CRST
CIO, CC4, CC8
CCLK
I/O, C4, C8
2
AT83C24
4234C–SCR–04/04
AT83C24
Pin Description
Pinout (Top View)
AT83C24 28-pin SOIC Pinout
C8
DVCC
RESET
CMDVCC
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
PRES/INT
C4
I/O
EVCC
A2/CK
A1 /RST
A0 /3V
SCL
SDA
QFN28 pinout
PRES/INT
RESET
DVCC
CLK
CMDVCC
VSS
28 27 26 25 24 23 22
1
21
20
2
3
4
5
6
7
8
QFN 28
TOP VIEW
19
18
17
16
C8
I/O
EVCC
A2 /CK
A1 /RST
A0 /3V
SCL
VCC
CVSS
LI
CVCC
CVCCin
CRST
CCLK
V
CC
CVSS
LI
NC
CIO
CC8
CPRES
CVCC
CVCCin
SDA
15
NC
9 10 11 12 13 14
CRST
CCLK
CPRES
C4
CC8
NC
CC4
Note:
NC = Not Connected
Signals
Table 1.
Ports Description
Pad Name
Pad Internal
Power Supply
ESD
Limits
Pad
Type
Description
Microcontroller Interface Function:
A2/CK-
A1/RST-
A0/3V
EVCC
3 kV
I
TWI bus slave address selection input.
A2 and A1 pins are respectively connected to CCLK and CRST signals in “transparent
mode” (see Transparent mode § page 16).
The slave address of the device is based on the value present on A2, A1, A0 on the
rising edge of RESET pin (see Table 2).
Microcontroller Interface Function:
PRES/INT
EVCC
3 kV
O
open-
drain
Depending on IT_SEL value (see CONFIG4 register),
PRES/INT outputs card presence status or interruptions (see Interrupts § page 9)
An internal Pull-up to EVCC can be activated in the pad if necessary using INT_PULLUP
bit (CONFIG4 register).
Microcontroller Interface Function:
•
•
I/O
RESET
V
CC
3 kV
open-
drain
•
•
Power-on reset
A low level on this pin keeps the AT83C24 under reset even if applied on power-on.
It also resets the AT83C24 if applied when the AT83C24 is running.
Asserting RESET when the chip is in Shut-down mode returns the chip to normal
operation.
AT83C24 is driving the Reset pin Low on power-on-reset or if power fail on V
CC
or
DVCC (see POWERMON bit in CONFIG4 register), this can be used to reset or
interrupt other devices. After reset, AT83C24 needs to be reconfigured before
starting a new card session.
SDA
V
CC
3 kV
I/O
open-
drain
I/O
open-
drain
Microcontroller Interface Function
TWI serial data
SCL
V
CC
3 kV
Microcontroller Interface Function
TWI serial clock
CC4
CIO
NC
3
4234C–SCR–04/04
Table 1.
Ports Description (Continued)
Pad Name
Pad Internal
Power Supply
ESD
Limits
Pad
Type
Description
Microcontroller Interface Function
I/O
EVCC
3 kV
Copy of CIO pin and high level reference for EVCC.
I/O
I/O is the reference level for EVCC after power up.
If an external power supply is on EVCC pin, I/O should not be kept above EVCC for an
extended time.
C4
EVCC
3 kV
I/O
Microcontroller Interface Function
(pull-up) Copy of Card CC4.
3 kV
I/O
Microcontroller Interface Function
C8
EVCC
(pull-up) Copy of Card CC8.
3 kV
I
I/O
Microcontroller Interface Function
Master Clock
Smart card interface function
CLK
EVCC
CIO
CVCC
8 kV+
(pull-up) Card I/O
I/O
Smart card interface function
CC4
CVCC
8 kV+
(pull-up) Card C4
I/O
Smart card interface function
CC8
CVCC
8 kV+
(pull-up) Card C8
Smart card interface function
CPRES
V
CC
8 kV+
I
Card presence
(pull-up) An internal Pull-up to VCC can be activated in the pad if necessary using PULLUP bit
(CONFIG1 register).
O
Smart card interface function
Card clock
Smart card interface function
Card reset
Microcontroller Interface Function:
Activation/Shutdown of the smart card Interface.
Supply Voltage
V
CC
is used to power the internal voltage regulators and I/O buffers.
DC/DC Input
LI
must be
tied to V
CC
pin through an external coil (typically 4.7
µH)
and provides the
current for the charge pump of the DC/DC converter.
It may be directly connected to V
CC
if the step-up converter is not used (see STEPREG
in CONFIG4 register and see minimum VCC value in Table 16 (class A) and table 17
(class B)).
Card Supply Voltage
CCLK
CVCC
8 kV+
CRST
CVCC
8 kV+
O
I
(pull-up)
CMDVCC
EVCC
3 kV+
VCC
3 kV+
PWR
LI
3 kV+
PWR
CVCC
8 kV+
PWR
CVCC is the programmable voltage output for the Card interface.
It must be connected to an external decoupling capacitor.
CVCCin
8 kV+
PWR
Card Supply Voltage
This pin must be connected to CVCC.
4
AT83C24
4234C–SCR–04/04
AT83C24
Table 1.
Ports Description (Continued)
Pad Name
Pad Internal
Power Supply
ESD
Limits
Pad
Type
Description
Digital Supply Voltage
DVCC
3 kV+
PWR
Is internally generated and used to supply the digital core.
This pin has to be connected to an external capacitor of 100 nF and should not be
connected to other devices.
Extra Supply Voltage (Microcontroller power supply)
EVCC is used to supply the level shifters of host interface pins.
EVCC
3 kV+
PWR
EVCC voltage can be supplied from the external EVCC pin.
It can also be generated internally by an automatic follow up of the logic high level on the
I/O pin. In this configuration, connect a 100 nF + 100kOhms in parallel between EVCC
pin and VSS pin.
CVSS
VSS
8 kV+
GND
GND
DC/DC Ground
CVSS is used to sink high shunt currents from the external coil.
Ground
5
4234C–SCR–04/04
京公网安备 11010802033920号
EEWORLD
