ST92F250CV2T6 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> ST92F250CV2T6

ST92F250CV2T6: Description16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，523 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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ST92F250CV2T6 Overview

16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100

ST92F250CV2T6 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	14 X 14 MM, ROHS COMPLIANT, LQFP-100
Contacts	100
Reach Compliance Code	compli
Has ADC	YES
Address bus width	22
bit size	16
CPU series	ST9
maximum clock frequency	5 MHz
DAC channel	NO
DMA channel	YES
External data bus width	8
JESD-30 code	S-PQFP-G100
JESD-609 code	e4
length	14 mm
Number of I/O lines	77
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	8192
rom(word)	262144
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	24 MHz
Maximum slew rate	60 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	HCMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST92F124xx/ST92F150Cxx/

ST92F150JDV1/ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM,

E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

Datasheet

−

production data

Features

■

Memories

– Internal memory: Single Voltage Flash up to 256

Kbytes, RAM up to 8 Kbytes, 1 Kbyte E

3 TM

(Emulated EEPROM)

– In-Application Programming (IAP)

– 224 general purpose registers (register file)

available as RAM, accumulators or index

pointers

Clock, reset and supply management

– Register-oriented 8/16 bit CORE with RUN,

WFI, SLOW, HALT and STOP modes

– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V

range

– PLL Clock Generator (3-5 MHz crystal)

– Minimum instruction time: 83 ns (24 MHz int.

clock)

Up to 80 I/O pins

Interrupt management

– 4 external fast interrupts + 1 NMI

– Up to 16 pins programmable as wake-up or

additional external interrupt with multi-level

interrupt handler

DMA controller for reduced processor overhead

Timers

– 16-bit Timer with 8-bit Prescaler, and Watchdog

Timer (activated by software or by hardware)

– 16-bit Standard Timer that can be used to

generate a time base independent of PLL Clock

Generator

– Two 16-bit independent Extended Function

Timers (EFTs) with Prescaler, up to two Input

Captures and up to two Output Compares

– Two 16-bit Multifunction Timers, with Prescaler,

up to two Input Captures and up to two Output

Compares

Communication interfaces

– Serial Peripheral Interface (SPI) with selectable

Master/Slave mode

■

LQFP64

14x14

PQFP100

14x20

LQFP100

14x14

■

– One Multiprotocol Serial Communications

Interface with asynchronous and synchronous

capabilities

– One asynchronous Serial Communications

Interface with 13-bit LIN Synch Break

generation capability

– J1850 Byte Level Protocol Decoder (JBLPD)

– Up to two full I²C multiple Master/Slave

Interfaces supporting Access Bus

– Up to two CAN 2.0B Active interfaces

■

Analog peripheral (low current coupling)

– 10-bit A/D Converter with up to 16 robust input

channels

Development tools

– Free High performance development

environment (IDE) based on Visual Debugger,

Assembler, Linker, and C-Compiler; Real Time

Operating System (OSEK OS, CMX) and CAN

drivers

– Hardware emulator and Flash programming

board for development and ISP Flasher for

production

Device summary

Part number

ST92F124R1, ST92F124R9,

ST92F124V1

ST92F150CR1, ST92F150CR9,

ST92F150CV1, ST92F150CV9

ST92F150JDV1

ST92F250CV2

■

Table 1.

Reference

ST92F124xx

ST92F150Cxx

ST92F150JDxx

ST92F250Cxx

■

July 2012

This is information on a product in full production.

Doc ID 8848 Rev 7

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www.st.com

Contents

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1

2.2

I/O port alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Termination of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1

Alternate functions for I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1

6.2

Core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.2.1

6.2.2

6.3

System registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

Central interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Paged registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Stack pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.4

6.5

6.6

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Address space extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.6.1

6.6.2

Addressing 16-Kbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Addressing 64-Kbyte segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.7

MMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.7.1

6.7.2

6.7.3

DPR[3:0]: data page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

CSR: Code segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

ISR: Interrupt segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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Contents

DMASR: DMA segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.8

MMU usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.8.1

6.8.2

6.8.3

Normal program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Single voltage Flash and E3™ (emulated EEPROM) . . . . . . . . . . . . . . 75

7.1

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

EEPROM emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

E3 TM update operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Important note on Flash erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 79

7.3

7.3.1

7.3.2

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

7.4

7.5

Write operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.5.1

7.5.2

Non volatile registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.6

Flash in-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.6.1

Code update routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.1

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.2.1

8.2.2

Reset vector location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Location of vector for external watchdog refresh . . . . . . . . . . . . . . . . . . 95

8.3

ST92F124/F150/F250 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

9.1

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

9.1.1

On-chip peripheral interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Interrupt vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

9.2.1

Divide by zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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Contents

9.2.2

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

Segment paging during interrupt routines . . . . . . . . . . . . . . . . . . . . . . 123

9.3

9.4

Interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Priority level arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.4.1

9.4.2

9.4.3

9.4.4

Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Simultaneous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Dynamic priority level modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.5

Arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.5.1

9.5.2

Concurrent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

9.6

9.7

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Standard interrupts (CAN and SCI-A) . . . . . . . . . . . . . . . . . . . . . . . . . . 135

9.7.1

9.7.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Important note on standard interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.8

9.9

9.10

9.11

9.12

Top level interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Dedicated on-chip peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 137

Interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Wake-up / interrupt lines management unit (WUIMU) . . . . . . . . . . . . . . 149

9.12.1

9.12.2

9.12.3

9.12.4

9.12.5

9.12.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Important note on WUIMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

On-chip direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . 159

10.1

10.2

10.3

10.4

10.5

10.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

DMA priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

DMA cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Swap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Reset and clock control unit (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . 165

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Contents

11.1

11.2

11.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

11.2.1

Clock control unit overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

11.3.6

PLL clock multiplier programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

PLL free running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

CPU clock prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Peripheral clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11.4

11.5

11.6

Clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Reset/stop manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

11.6.1

Reset pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

External memory interface (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12.1

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

External memory signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.2.7

12.2.8

AS: Address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

DS: Data strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

RW: Read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

DS2: Data strobe 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

PORT 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

PORT 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

PORT 9 [7:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

WAIT: External memory wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.3

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

13.1

13.2

13.3

13.4

13.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

13.5.1

13.5.2

Pin declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Pin declared as an alternate function input . . . . . . . . . . . . . . . . . . . . . 200

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810 computer motherboard circuit diagram_26

Please help analyze the TL431 circuit: [i=s]This post was last edited by Baboerben on 2022-1-4 08:25[/i]I have some doubts about a circuit, please explain it to me 1. What is the function of R24 in the figure below? 2. What are the functio...; 灞波儿奔 Power technology

TI store "Cyber Monday" big sale, 10% off all development tools + free shipping!: [size=3]What to do if you missed "Double Eleven" and "Black Friday"? Don't worry[/size][size=3] [/size] [size=3]TI store starts a week-long "Cyber Monday" event from today! [/size] [url=http://s441910...; eric_wang TI Technology Forum

Calling software disk under evc 4.0: How to call the soft keyboard under evc4.0? The header file already includes #include "Sipapi.h". In Edit, getting focus and losing focus are written like this: void student::OnSetfocusEdit1() { HWND ...; weimeng4359 Embedded System

2440 nandflash startup problem: [size=16px]When booting from nandflash, the first 4k of RAM should be the same as nand. However, in ram, 66 bytes from 200h are FF. The same is true for the rest. Later, I burned a larger program into...; 竹子 Embedded System

Make a beautiful e-magazine by yourself: I believe many of you have downloaded those beautiful electronic magazines. While enjoying the beautiful pictures and music, do you think it is very troublesome to make such electronic magazines? In f...; manyi RF/Wirelessly

Let me teach you how to make a digital controlled amplifier: [i=s] This post was last edited by Jixia Mujin on 2014-7-5 21:51 [/i] I was busy completing the course design some time ago. Now I am on vacation and have passed the course design defense. I would lik...; 季夏木槿 MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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