ST7PLITEUS2U6TR datasheet, PDF

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ST7PLITEUS2U6TR: Description8-bit MCU with single voltage Flash memory, ADC, timers; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，136 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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ST7PLITEUS2U6TR Overview

8-bit MCU with single voltage Flash memory, ADC, timers

ST7PLITEUS2U6TR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	DFN
package instruction	LEAD FREE, DFN-8
Contacts	8
Reach Compliance Code	compli
Has ADC	NO
Other features	ALSO OPERATES AT 2.4V MINIMUM SUPPLY AT 4 MHZ
Address bus width
bit size	8
CPU series	ST72
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	R-XDSO-N8
length	4.5 mm
Number of I/O lines	5
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	UNSPECIFIED
encapsulated code	VSON
Encapsulate equivalent code	SOLCC8,.12,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	128
rom(word)	1024
ROM programmability	MROM
Maximum seat height	1 mm
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	3.3 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	3.5 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST7LITEUS2

ST7LITEUS5

8-bit MCU with single voltage Flash memory, ADC, timers

Features

■

Memories

– 1 Kbytes single-voltage Flash Program

memory with readout protection, ICP and

IAP)

10 K write/erase cycles guaranteed

data retention: 20 years at 55 °C

– 128 bytes RAM

Clock, Reset and Supply management

– 3-level low-voltage supervisor (LVD) and

auxiliary voltage detector (AVD) for safe

power-on/off

– Clock sources: internal trimmable 8 MHz

RC oscillator, internal low power, low

frequency RC oscillator or external clock

– Five power saving modes: Halt, Auto-

wakeup from Halt, Active-halt, Wait, Slow

Plastic DIP8

■

SO8

150”

DFN8

Plastic DIP16

■

2 Timers

– One 8-bit Lite timer (LT) with prescaler

including: watchdog, one realtime base and

one 8-bit input capture.

– One 12-bit auto-reload timer (AT) with

output compare function and PWM

A/D Converter

– 10-bit resolution for 0 to V

– 5 input channels

■

)

-O

■

Interrupt management

– 11 interrupt vectors plus TRAP and RESET

– 5 external interrupt lines (on 5 vectors)

I/O ports

– 5 multifunctional bidirectional I/O lines

– 1 additional Output line

– 6 alternate function lines

– 5 high sink outputs

Device summary

■

Instruction Set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode

detection

– 17 main addressing modes

– 8x8 unsigned multiply instruction

Development Tools

– Full hardware/software development

package

– Debug module

Table 1.

Features

ST7LITEUS2

ST7LITEUS5

Program memory

RAM (stack)

Peripherals

ADC

1 Kbytes

128 (64) bytes

LT Timer w/ Wdg, AT Timer w/ 1 PWM

10-bit

Operating Supply

CPU Frequency

2.4 to 3.3 V @f

CPU

=4 MHz, 3.3 to 5.5 V @f

CPU

=8 MHz

up to 8 MHz RC

-40 to +85 °C / -40 to 125 °C

SO8 150”, Pastic DIP8, DFN8, Pastic DIP16

(1)

Operating Temperature

Packages

1. For development or tool prototyping purposes only. Not orderable in production quantities.

February 2009

Rev 5

1/136

www.st.com

Contents

ST7LITEUS2, ST7LITEUS5

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.1

4.3.2

In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

In application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.4

4.5

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.5.1

4.5.2

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Flash Write/Erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

)

-O

4.6

4.7

4.7.1

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

5.2

5.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.1

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.2

5.3.3

5.3.4

5.3.5

Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

6.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/136

ST7LITEUS2, ST7LITEUS5

Contents

6.3

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

Main Clock Control/Status register (MCCSR) . . . . . . . . . . . . . . . . . . . . 30

RC Control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

System Integrity (SI) Control/status register (SICSR) . . . . . . . . . . . . . . 31

AVD Threshold Selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . 32

Clock Controller Control/Status register (CKCNTCSR) . . . . . . . . . . . . . 32

6.4

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

External Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 36

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5

6.5.1

6.5.2

Multiplexed I/O Reset Control register 1 (MUXCR1) . . . . . . . . . . . . . . . 37

Multiplexed I/O Reset Control register 0 (MUXCR0) . . . . . . . . . . . . . . . 37

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1

Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.3.1

7.3.2

External Interrupt Control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 41

External Interrupt Control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 42

)

-O

7.2

7.3

7.4

7.4.1

7.4.2

7.4.3

7.4.4

Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.1

8.2

8.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.4.1

8.4.2

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.4

8.5

Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3/136

Contents

8.5.1

ST7LITEUS2, ST7LITEUS5

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.1

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2.1

9.2.2

9.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.3

9.4

9.5

9.6

Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1

Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.1

10.1.2

10.1.3

10.1.4

10.1.5

10.1.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

)

-O

10.2

10.2.1

10.2.2

10.2.3

10.2.4

10.2.5

10.2.6

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12-bit auto-reload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3

10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.3.1

10.3.2

10.3.3

10.3.4

10.3.5

10.3.6

4/136

ST7LITEUS2, ST7LITEUS5

Contents

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1

ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1.1

11.1.2

11.1.3

11.1.4

11.1.5

11.1.6

11.1.7

Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.1

Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.1

12.1.2

12.1.3

12.1.4

12.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

)

-O

12.2

12.3

12.3.1

12.3.2

12.3.3

12.3.4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . 95

Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . 96

Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.4

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

12.4.1

12.4.2

12.4.3

Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Internal RC oscillator supply current characteristics . . . . . . . . . . . . . . 100

12.5

Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 105

Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 106

12.6

12.7

12.7.1

12.7.2

12.7.3

12.8

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5/136

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