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ST72T511R6T3S

Description
8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size942KB,164 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
Download Datasheet Parametric View All

ST72T511R6T3S Overview

8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

ST72T511R6T3S Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeQFP
package instruction14 X 14 MM, TQFP-64
Contacts64
Reach Compliance Codecompli
Has ADCYES
Other featuresOPERATES AT 3V MIN SUPPLY @ 8 MHZ
Address bus width
bit size8
CPU seriesST72
maximum clock frequency16 MHz
DAC channelNO
DMA channelNO
External data bus width
JESD-30 codeS-PQFP-G64
length14 mm
Number of I/O lines48
Number of terminals64
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP64,.6SQ,32
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3/5 V
Certification statusNot Qualified
RAM (bytes)1024
rom(word)32768
ROM programmabilityOTPROM
Maximum seat height1.6 mm
speed8 MHz
Maximum slew rate20 mA
Maximum supply voltage5.5 V
Minimum supply voltage3.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
ST72311R, ST72511R,
ST72512R, ST72532R
8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC,
16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
DATASHEET
s
s
s
s
s
Memories
– 16K to 60K bytes Program memory
(ROM,OTP and EPROM)
with read-out protection
– 256 bytes E
2
PROM Data memory
(only on ST72532R4)
– 1024 to 2048 bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system
– Low voltage supply supervisor
– Clock sources: crystal/ceramic resonator os-
cillator or external clock
– Beep and Clock-out capability
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
Interrupt Management
– Nested interrupt controller
– 13 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
– TLI dedicated top level interrupt pin
48 I/O Ports
– 48 multifunctional bidirectional I/O lines
– 32 alternate function lines
– 12 high sink outputs
5 Timers
– Configurable watchdog timer
– Real time clock timer
– One 8-bit auto-reload timer with 4 independ-
ent PWM output channels, 2 input captures,
output compares and external clock with
event detector (except on ST725x2R4)
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and Pulse generator modes
TQFP64
14 x 14
s
s
s
s
3 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
– CAN interface (except on ST72311Rx)
1 Analog peripheral
– 8-bit ADC with 8 input channels
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
Development Tools
– Full hardware/software development package
Device Summary
Features
ST72511R9 ST72511R7 ST72511R6
ST72311R9 ST72311R7 ST72311R6 ST72512R4
ST72532R4
Program memory - bytes
60K
48K
32K
60K
48K
32K
16K
16K
RAM (stack) - bytes
2048 (256) 1536 (256) 1024 (256) 2048 (256) 1536 (256) 1024 (256) 1024 (256)
1024 (256)
EEPROM - bytes
-
-
-
-
-
-
-
256
watchdog, two 16-bit timers, 8-bit PWM watchdog, two 16-bit timers, 8-bit PWM watchdog, two 16-bit timers,
Peripherals
ART, SPI, SCI, CAN, ADC
ART, SPI, SCI, ADC
SPI, SCI, CAN, ADC
Operating Supply
3.0V to 5.5V
3.0 to 5.5V
1)
CPU Frequency
2 to 8 MHz (with 4 to 16 MHz oscillator)
2 to 4 MHz
1)
Operating Temperature
-40°C to +85°C (-40°C to +105/125°C optional)
Packages
TQFP64
Note
1. See Section 12.3.1 on page 133 for more information on V
DD
versus f
OSC
.
Rev. 2.1
February 2000
1/164
1
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