IDT71V2577YS80BGG datasheet, PDF

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IDT71V2577YS80BGG: DescriptionCache SRAM, 128KX36, 8ns, CMOS, PBGA119, BGA-119; Categorystorage; File Size626KB，22 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V2577YS80BGG Overview

Cache SRAM, 128KX36, 8ns, CMOS, PBGA119, BGA-119

IDT71V2577YS80BGG Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Is Samacsys	N
Maximum access time	8 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	2.36 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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128K x 36, 256K x 18

3.3V Synchronous SRAMs

2.5V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Features

◆

IDT71V2577S

IDT71V2579S

IDT71V2577SA

IDT71V2579SA

Description

The IDT71V2577/79 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V2577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

4877 tbl 01

◆

128K x 36, 256K x 18 memory configurations

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

NOTE:

and

are not applicable for the IDT71V2579.

JUNE 2003

DSC-4877/08

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