DEMO MANUAL DC1774A-A
LTC6430-15
100MHZ to 300MHZ Differential
ADC
Driver/IF
Amplifier
Description
Demonstration circuit 1774A-A is a differential ADC
driver/IF amplifier featuring the
LTC
®
6430-15.
It is part
of the DC1774A demo board family supporting the
LTC643X-YY amplifier series. The DC1774A-A is opti-
mized for a frequency range of 100MHz to 300MHz and
utilizes a minimum of passive external components to
configure the amplifier for this application.
Because the LTC6430-15 has 100Ω differential input and
output impedance, the demo circuit uses transformers to
convert the impedance to 50Ω single-ended allowing easy
evaluation with commercially available RF test equipment.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
performance summary
SYMBOL
Power Supply
V
CC
I
CC
Operating Supply Range
Current Consumption
PARAMETER
Specifications are at T
A
= 25°C, V
CC
= 5V
VALUE / UNIT
4.75V to 5.25V
160mA
CONDITIONS
All V
CC
Pins Plus OUT Pins
Total Current
Frequency
(MHz)
50
100
200
240
300
400
Power Gain
|
S21
|
(dB)
13.1
14.5
14.5
14.2
13.6
12.2
Output
Output
Third-Order
Third-Order
Intercept Point
1
Intermodulation
1
OIP3
(dBm)
47.1
47.3
47.2
50.0
47.0
46.4
OIM3
(dBc)
–90.2
–90.5
–90.3
–96.0
–90.0
–88.8
Second
Harmonic
Distortion
2
HD2
(dBc)
–83.3
–84.6
–86.6
–83.8
(4)
Third Harmonic
Distortion
2
HD3
(dBc)
–93.1
–95.3
–90.9
–85.2
(4)
–83.4
(4)
–85.0
(4)
Output 1dB
Compression
Point
P1dB
(dBm)
21.8
22.6
22.2
22.2
22.0
21.3
Noise Figure
3
NF
(dB)
5.2
4.1
4.0
4.1
4.4
5.1
–73.6
(4)
–56.1
(4)
All figures are referenced to J7 (input port) and J8 (output port).
Note 1:
Two-tone test condition: Output power level = 2dBm/tone;
tone spacing = 1MHz.
Note 2:
Single-tone test condition: Output power level = 8dBm.
Note 3:
Small signal noise figure.
Note 4:
Performance degraded due to transformers’ being out of working
frequency range.
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DEMO MANUAL DC1774A-A
Block Diagram
GND
8, 14, 17, 23
AND PADDLE 25
V
CC
9, 22
BIAS AND TEMPERATURE
COMPENSATION
24
+IN
+OUT
18
T_DIODE
16
7
–IN
– OUT
13
GND
8, 14, 17, 23 AND PADDLE 25
dc1774aa F01
Figure 1. LTC6430-15 Device Block Diagram
operation
Demo Circuit 1774A-A is a highly linear fixed-gain ampli-
fier. The LTC6430-15 is internally matched to a 100Ω
differential source and load impedance from 20MHz to
1300MHz. Due to the unpopularity of 100Ω differential
test equipment, transformers have been added to convert
impedance from differential 100Ω to single-ended 50Ω
for the input and the output ports. The frequency range
of the circuit is limited by the balun transformers. Hence,
this demo board works best with a frequency range from
100MHz to 300MHz. Figure 2 shows the performance of
the demo board.
NOMINAL WORKING
FREQUENCY RANGE
18
16
14
|S21| (dB)
12
10
8
6
4
0
100
200
FREQUENCY (MHz)
300
|S12|
|S21|
|S11|
|S22|
0
–4
–8
–12
–16
–20
–24
–28
400
dc1774aa F02
Figure 2. Demo Board DC1774A-A S-Parameters
|S11,|S12|,|S22| (dB)
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DEMO MANUAL DC1774A-A
operation
Figure 3 shows the simplified demo circuit schematic. It
requires a minimum of passive supporting components.
The 2:1 transformers convert the differential to single-
ended 50Ω for compatibility with most test equipment.
The input and output DC-blocking capacitors (C1, C2,
C3 and C4) are required because this device is inter-
nally biased for optimal operation. The frequency appropri-
ate choke (L1 and L2) and the decoupling capacitors (C5,
C21, C22 and C23) provide bias to the RF ±OUT nodes. Only
a single 5V supply is necessary for V
CC
pins on the device.
An optional input stability network has been added. It
consists of a parallel 62pF (C8 and C9) and 348Ω (R1
and R2) input network to insure low frequency stability.
Table 1 shows the function of each input and output on
the board.
Table 1. DC1774A-A Board I/O Descriptions
CONNECTOR
J7 (+IN)
FUNCTION
Single-Ended Input.
Impedance-matched to 50Ω. Drive from a
50Ω network analyzer or signal source.
Single-Ended Output.
Impedance-matched to 50Ω. Drive from a
50Ω network analyzer or spectrum analyzer.
Positive Supply Voltage Source.
Negative Supply Ground.
J8 (–OUT)
E3 or J11 (V
CC
)
E6 or J18 (GND)
Stability Network
C8
62pF
R2
348
25
24
23
22
21
20
19
VCC
C7
1000pF
VCC
C1
1000pF
L1
560nH
C22
0.1uF
C3
1000pF
C21
1000pF
R4
0
0603
GND
GND
DNC
J7
+IN
SMA
T3 = ADT2-1T+
1
6
5
3
4
C14
1000pF
DNC
DNC
+IN
VCC
1
2
3
4
5
6
DNC
DNC
DNC
DNC
DNC
DNC
U1
+OUT
GND
T_DIODE
DNC
GND
18
17
16
15
14
13
OPT
R19
T4 = ADT2-1T+
4
C15
1000pF
5
6
1
SMA
3
U1 = LTC6430-15
GND
DNC
DNC
DNC
VCC
-IN
C4
1000pF
J8
-OUT
-OUT
R3
0
0603
C2
1000pF
10
11
12
C9
62pF
R1
348
VCC
L2
560nH
VCC
7
8
9
J11
+5V
E3
C23
0.1uF
C5
1000pF
J18
GND
E6
+5V
Stability Network
C20
1000pF
GND
Figure 3. Simplified Demo Board DC1774A-A Schematic
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DEMO MANUAL DC1774A-A
operation
Additional Information
The particular element values shown in the demo board
schematic are chosen for wide bandwidth operation.
Depending on the desired frequency, performance may
be improved by the proper selection of these supporting
components.
As with any RF device, minimizing ground inductance
is critical. Care should be taken with the board layout
because of these exposed pad packages. The maximum
number of minimum diameter vias holes should be placed
underneath the exposed pad. This will ensure good RF
ground and low thermal impedance. Maximizing the
copper ground plane will also improve heat spreading
and low inductance. It is a good idea to cover the via
holes with solder mask on the back side of the PCB to
prevent solder from wicking away from the critical PCB
to the exposed pad interface.
The DC1774A-A has a nominal working frequency range
from 100MHz to 300MHz. It is not intended for operation
down to DC. The lower frequency cutoff is limited by on-
chip matching elements.
Figure 6 shows the generic PCB schematic for the
LTC643X-YY amplifier series. The board can be modi-
fied for multiple demo board versions. For example,
both DC1774A-A and DC1774A-B demo boards have a
differential amplifier at U1, therefore, the board is using
transformers to transform from differential to single-
ended input and output. Likewise, the DC1774A-C is a
single-ended demo board; it uses the LTC6431-15 for
single-ended input and output.
setup anD testing signal sources
The LTC6430-15 is an amplifier with high linearity per-
formance, therefore output intermodulation products are
very low. For this reason, it drives most test equipment
and test setups to their limits. Consequently, accurate
measurement of the third-order intercept point for a low
distortion IC such as the LTC6430-15 requires certain
precautions to be observed in the test setup and testing
procedure.
SETUP SIGNAL SOURCES
Figure 5 shows a proposed IP3 test setup. This setup has
low phase noise, good reverse isolation, high dynamic
range, sufficient harmonic filtering and wideband imped-
ance matching. The setup is outlined here:
a. High performance signal generators 1 and 2 (HP8644A)
should be used in the setup. These suggested genera-
tors have low harmonic distortion and very low phase
noise.
b. High linearity amplifiers to improve isolation. They
prevent the two signal generators from crosstalking
with each other and provide higher output power.
c. A lowpass filter to suppress harmonic contents from
interfering with the test signal.
d. The signal combiner (from Mini-Circuits, ADP-2-9)
combines the two isolated input signals. This combiner
has a typical isolation of 27dB. For better VSWR and
isolation, use the H-9 signal combiner from M/A-COM,
which features >40dB isolation and a wider frequency
range. Passive devices (e.g., combiners) with magnetic
elements can contribute nonlinearity to the signal chain
and should be used cautiously.
e. The attenuator pads, on all three ports of the signal
combiner, will support further isolation of the two input
signal sources. They will reduce reflection and promote
maximum power transfer with wideband impedance
matching.
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DEMO MANUAL DC1774A-A
setup anD testing signal sources
TESTING SIGNAL SOURCES
The testing signal should be evaluated and optimized before
it is used for measurements. The following outlines the
necessary steps to achieve optimization:
a. Apply two independent signals, f1 and f2, from signal
generator 1 and signal generator 2 at 240MHz and
241MHz while setting amplitude = –12dBm per tone
at the combined output.
b. Connect the combined signal directly to the spectrum
analyzer (without the DUT).
c. Adjust the spectrum analyzer for the maximum possible
resolution of the intermodulation products amplitude
in dBc relative to the main tone power. A narrower
resolution bandwidth will take a longer time to sweep.
Optimize the dynamic range of the spectrum analyzer
by adjusting input attenuation.
First increase the spectrum analyzer input attenuation
(normally in steps of 5dB or 10dB). If the IMD product
levels decrease when the input attenuation is increased,
then the input power level was too high for the spectrum
analyzer to make a valid measurement. In other words,
the spectrum analyzer 1st mixer was overloaded and
producing its own IMD products. If the IMD reading
holds constant with increased input attenuation, then
a sufficient amount of attenuation was present. Adding
too much attenuation will raise the noise floor and bury
the intended IMD signal. Therefore, select just enough
attenuation to achieve a stable and valid measurement.
d. In order to achieve a valid measurement result, the
test system must have lower distortion than the DUT
intermodulation. For example, to measure a 47dBm
OIP3, the measured intermodulation products will be
–90dBc below the –12dBm per tone input level and
the test system must have intermodulation products
approximately –96dBc or better. For best results, the
IMD or noise floor should be at least –100dBc before
connecting the DUT.
Testing the DUT
At this point, the input level has been established at
–12dBm per tone, and the input IMD from the test setup
is well suppressed at –96dBm max. Furthermore, the
spectrum analyzer is set up to measure very low level
IMD components.
a. Insert the DUT and output attenuator into the setup,
inline between the signal source and the spectrum
analyzer. The output attenuator should match the DUT
gain.
b. Fine tune the signal generator levels by a small amount
if necessary (<1dB), to keep output power at 2dBm per
tone at the amplifier output.
c. Measure the output IMD level using the same optimized
setup as previous. Based on the output power level of
2dBm per tone, and knowing the IMD level, OIP3 can
be calculated.
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