74HC4351; 74HCT4351
Rev. 3 — 9 July 2018
8-channel analog multiplexer/demultiplexer with latch
Product data sheet
1
General description
The 74HC4351; 74HCT4351 is a single-pole octal-throw analog switch (SP8T) suitable
for use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features
three digital select inputs (S0 to S2), eight independent inputs/outputs (Yn), a common
input/output (Z) and two digital enable inputs (E1 and E2). With E1 LOW and E2 HIGH,
one of the eight switches is selected (low impedance ON-state) by S0 to S2. The data
at the select inputs may be latched by using the latch enable input (LE). When LE is
HIGH the latch is transparent. When E1 is HIGH or E2 is LOW all 8 analog switches are
turned off. Inputs include clamp diodes. This enables the use of current limiting resistors
to interface inputs to voltages in excess of V
CC
.
2
Features and benefits
•
Wide analog input voltage range from -5 V to +5 V
•
Complies with JEDEC standard no. 7A
•
Low ON resistance:
–
80 Ω (typical) at V
CC
- V
EE
= 4.5 V
–
70 Ω (typical) at V
CC
- V
EE
= 6.0 V
–
60 Ω (typical) at V
CC
- V
EE
= 9.0 V
•
Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
•
Typical ‘break before make’ built-in
•
Address latches provided
•
ESD protection:
–
HBM JESD22-A114F exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V
–
CDM JESD22-C101E exceeds 1000 V
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3
Applications
•
Analog multiplexing and demultiplexing
•
Digital multiplexing and demultiplexing
•
Signal gating
Nexperia
8-channel analog multiplexer/demultiplexer with latch
74HC4351; 74HCT4351
4
Ordering information
Package
Temperature range
Name
SO20
SSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
Version
SOT163-1
SOT339-1
-40 °C to +125 °C
-40 °C to +125 °C
Table 1. Ordering information
Type number
74HC4351D
74HCT4351D
74HC4351DB
74HCT4351DB
5
Functional diagram
20
V
CC
Y0
17
15
13
12
S0
S1
S2
Y1
18
Y2
LE
Y3
LOGIC
LEVEL
CONVERSION
AND LATCHES
19
11
16
1-OF-8
DECODER
Y4
1
Y5
6
Y6
7
8
E1
E2
Y7
2
5
Z
GND
10
9
V
EE
aaa-028752
4
Figure 1. Functional diagram
74HC_HCT4351
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2018
2 / 25
Nexperia
8-channel analog multiplexer/demultiplexer with latch
74HC4351; 74HCT4351
15
13
12
7
0
2D, 1 X
2
&
C2
MUX/DMUX
0
1
2
4
3
4
5
6
7
G1
0
7
15
13
12
S0
S1
S2
Y0
Y1
Y2
Y3
17
18
19
16
1
6
2
5
8
9
17
18
19
16
1
6
2
5
11
LE
Y4
Y5
7
8
E1
E2
Z
4
Y6
Y7
aaa-028753
aaa-028754
Figure 2. Logic symbol
Figure 3. IEC logic symbol
Y
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
Z
V
EE
001aad544
Figure 4. Schematic diagram (one switch)
74HC_HCT4351
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2018
3 / 25
Nexperia
8-channel analog multiplexer/demultiplexer with latch
74HC4351; 74HCT4351
6
Pinning information
6.1 Pinning
74HC4351
74HCT4351
Y4
Y6
n.c.
Z
Y7
Y5
E1
E2
V
EE
1
2
3
4
5
6
7
8
9
20 V
CC
19 Y2
18 Y1
17 Y0
16 Y3
15 S0
14 n.c.
13 S1
12 S2
11 LE
aaa-028755
74HC4351
74HCT4351
Y4
Y6
n.c.
Z
Y7
Y5
E1
E2
V
EE
1
2
3
4
5
6
7
8
9
20 V
CC
19 Y2
18 Y1
17 Y0
16 Y3
15 S0
14 n.c.
13 S1
12 S2
11 LE
aaa-028756
GND 10
GND 10
Figure 5. Pin configuration SOT163-1 (SO20)
Figure 6. Pin configuration SOT339-1 (SSOP20)
6.2 Pin description
Table 2. Pin description
Symbol
E1
E2
LE
S0, S1, S2
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7
Z
V
EE
GND
V
CC
n.c.
Pin
7
8
11
15, 13, 12
17, 18, 19, 16, 1, 6, 2, 5
4
9
10
20
3, 14
Description
enable input (active LOW)
enable input (active HIGH)
latch enable input (active LOW)
select inputs
independent input or output
common output or input
supply voltage
ground (0 V)
supply voltage
not connected
74HC_HCT4351
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2018
4 / 25
Nexperia
8-channel analog multiplexer/demultiplexer with latch
74HC4351; 74HCT4351
7
Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↓ = HIGH-to-LOW LE transition.
Input
E1
H
X
L
L
L
L
L
L
L
L
L
X
E2
X
L
H
H
H
H
H
H
H
H
H
X
LE
X
X
H
H
H
H
H
H
H
H
L
↓
S2
X
X
L
L
L
L
H
H
H
H
X
X
S1
X
X
L
L
H
H
L
L
H
H
X
X
S0
X
X
L
H
L
H
L
H
L
H
X
X
none
none
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
[1]
[2]
Channel ON
[1] Last selected channel “ON”.
[2] Select channels latched
8
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol Parameter
V
CC
I
IK
I
SK
I
SW
I
EE
I
CC
I
GND
T
stg
P
tot
P
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
power dissipation
SO20, SSOP20; T
amb
= -40 °C to +125 °C
per switch
[2]
Conditions
[1]
Min
-0.5
-
-
-
-
-
-50
-65
-
-
Max
+11.0
±20
±20
±25
±20
50
-
+150
500
100
Unit
V
mA
mA
mA
mA
mA
mA
°C
mW
mW
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
SW
< -0.5 V or V
SW
> V
CC
+ 0.5 V
-0.5 V < V
SW
< V
CC
+ 0.5 V
[1] To avoid drawing V
CC
current out of terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional switch must not
exceed 0.4 V. If the switch current flows into terminal Z, no V
CC
current will flow out of terminals Yn. In this case there is no limit for the voltage drop across
the switch, but the voltages at Yn and Z may not exceed V
CC
or V
EE
.
[2] For SO20 packages: above 70 °C the value of P
tot
derates linearly with 8 mW/K.
For SSOP20 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
74HC_HCT4351
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2018
5 / 25
京公网安备 11010802033920号
EEWORLD
