16 Mbit (x8/x16) Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
SST36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash
Data Sheet
FEATURES:
• Organized as 1M x16 or 2M x8
• Dual Bank Architecture for Concurrent
Read/Write Operation
– 16 Mbit Bottom Sector Protection
- SST36VF1601G: 4 Mbit + 12 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602G: 12 Mbit + 4 Mbit
• Single 2.7-3.6V for Read and Write Operations
• Superior Reliability
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
• Hardware Sector Protection/WP# Input Pin
– Protects the 4 outermost sectors (8 KWord)
in the smaller bank by driving WP# low and
unprotects by driving WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
array data
• Byte# Pin
– Selects 8-bit or 16-bit mode
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Chip-Erase Capability
• Block-Erase Capability
– Uniform 32 KWord blocks
• Erase-Suspend / Erase-Resume Capabilities
• Security ID Feature
– SST: 128 bits
– User: 256 Byte
• Fast Read Access Time
– 70 ns
• Latched Address and Data
• Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• Conforms to Common Flash Memory Interface (CFI)
• JEDEC Standards
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
– 56-ball LFBGA (8mm x 10mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF1601G and SST36VF1602G are 1M x16 or
2M x8 CMOS Concurrent Read/Write Flash Memory man-
ufactured with SST proprietary, high performance CMOS
SuperFlash memory technology. The split-gate cell design
and thick oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The devices write (Program or Erase) with a 2.7-3.6V
power supply and conform to JEDEC standard pinouts for
x8/x16 memories.
Featuring high performance Program, the SST36VF160xG
provide a typical Program time of 7 µsec and use Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
SST36VF160xG significantly improve performance and
reliability, while lowering power consumption. These
devices inherently use less energy during Erase and Pro-
gram than alternative flash technologies, because the total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. For any given voltage range,
the SuperFlash technology uses less current to program
and has a shorter erase time; therefore, the total energy
consumed during any Erase or Program operation is less
than alternative flash technologies.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
CSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
1
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high-density, surface-mount requirements, the
SST36VF1601G and SST36VF1602G devices are offered
in 48-ball TFBGA, 48-lead TSOP and 56-ball LFBGA
,
packages. See Figures 6, 7, and 8 for pin assignments.
The Read operation of the SST36VF160xG is controlled
by CE# and OE#, both of which have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The
data bus is in a high impedance state when either CE# or
OE# is high. Refer to Figure 9, the Read cycle timing dia-
gram, for further details.
Program Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, ensure that the sector which is
being programmed is fully erased.
The Program operation is accomplished in three steps:
1. Initiate Software Data Protection using the three-
byte load sequence.
2. Load address and data.
Device Operation
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
Auto Low Power Mode
These devices also have the
Auto Lower Power
mode
which puts them in a near-standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the typical I
DD
active Read current to 4 µA.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. Initiate the internal Program operation after the
rising edge of the fourth WE# or CE#, whichever
occurs first. The Program operation, once initi-
ated, will be completed typically within 7 µs.
See Figures 10 and 11 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 25 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
Concurrent Read/Write Operation
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank. See Table 1 below
for more information.
TABLE 1: Concurrent Read/Write State
Bank 1
Read
Read
Write
Write
No Operation
No Operation
Bank 2
No Operation
Write
Read
No Operation
Read
Write
Note:
For the purposes of this table, write means to perform Block-
or Sector-Erase or Program operations as applicable to the
appropriate bank.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
2
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Sector-Erase/Block-Erase Operation
The Sector- or Block- Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST36VF160xG offer both Sector-Erase and
Block-Erase operations.
The sector architecture is based on a uniform sector size of
2 KWord. The Sector-Erase operation is initiated by execut-
ing a six-byte command sequence with a Sector-Erase
command (50H) and sector address (SA) in the last bus
cycle.
The Block-Erase mode is based on a uniform block size of
32 KWord. Block-Erase is initiated by executing a six-byte
command sequence with Block-Erase command (30H) and
block address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (50H or 30H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase oper-
ation begins after the sixth WE# pulse.
Any commands issued during the Sector- or Block-Erase
operation are ignored except Erase-Suspend and Erase-
Resume. See Figures 15 and 16 for timing waveforms.
Erase-Suspend/Erase-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read or programmed into any sector or block that is not
engaged in an Erase operation. The operation is executed
by issuing a one-byte command sequence with Erase-Sus-
pend command (B0H). The device automatically enters
read mode no more than 10 µs after the Erase-Suspend
command had been issued. (T
ES
maximum latency equals
10 µs.) Valid data can be read from any sector or block that
is not suspended from an Erase operation. Reading at
address location within erase-suspended sectors/blocks
will output DQ
2
toggling and DQ
6
at ‘1’. While in Erase-Sus-
pend mode, a Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume a suspended Sector-Erase or Block-Erase
operation, the system must issue an Erase-Resume com-
mand. The operation is executed by issuing a one-byte
command sequence with Erase Resume command (30H)
at any address in the one-byte sequence.
Write Operation Status Detection
To optimize the system Write cycle time, the
SST36VF160xG provide two software means to detect the
completion of a Write (Program or Erase) cycle The soft-
ware detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system. Therefore, Data# Polling or
Toggle Bit maybe be read concurrent with the completion
of the write cycle. If this occurs, the system may possibly
get an incorrect result from the status detection process.
For example, valid data may appear to conflict with either
DQ
7
or DQ
6
. To prevent false results, upon detection of
failures, the software routine should loop to read the
accessed location an additional two times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the failure is valid.
Chip-Erase Operation
The SST36VF1601G and SST36VF1602G provide a
Chip-Erase operation, which erases the entire memory
array to the ‘1’ state. This operation is useful when the
entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com-
mands issued during the Chip-Erase operation are
ignored. See Table 6 for the command sequence, Figure
14 for timing diagram, and Figure 29 for the flowchart.
When WP# is low, any attempt to Chip-Erase will be
ignored.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
3
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Ready/Busy# (RY/BY#)
The SST36VF160xG include a Ready/Busy# (RY/BY#)
output signal. RY/BY# is an open drain output pin that indi-
cates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to V
DD
via an external
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling, and the device is then ready for the next
operation. For Sector-, Block-, or Chip-Erase, the toggle bit
(DQ
6
) is valid after the rising edge of sixth WE# (or CE#)
pulse. DQ
6
will be set to ‘1’ if a Read operation is attempted
on an Erase-Suspended Sector or Block. If Program oper-
ation is initiated in a sector/block not selected in Erase-Sus-
pend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector or block is being actively erased or erase-sus-
pended. Table 2 shows detailed bit status information. The
Toggle Bit (DQ
2
) is valid after the rising edge of the last
WE# (or CE#) pulse of Write operation. See Figure 13 for
Toggle Bit timing diagram and Figure 26 for a flowchart.
TABLE 2: Write Operation Status
Status
Normal
Standard
Operation Program
Standard
Erase
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Program
DQ
7
DQ7#
0
1
DQ
6
Toggle
Toggle
1
DQ
2
No Toggle
Toggle
Toggle
RY/BY#
0
0
1
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (V
IH
) the device is in x16 data configuration: all
data I/0 pins DQ
0
-DQ
15
are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic ‘0’, the device is in x8 data con-
figuration -- only data I/O pins DQ
0
-DQ
7
are active and con-
trolled by CE# and OE#. The remaining data pins DQ
8
-
DQ
14
are at Hi-Z, while pin DQ
15
is used as the address
input A
-1
for the Least Significant Bit of the address bus.
Data# Polling (DQ
7
)
When the SST36VF160xG are in an internal Program
operation, any attempt to read DQ
7
will produce the com-
plement of true data. Once the Program operation is com-
pleted, DQ
7
will produce valid data.
During internal Erase operation, any attempt to read DQ
7
will produce a ‘0’. Once the internal Erase operation is com-
pleted, DQ
7
will produce a ‘1’. The Data# Polling is valid
after the rising edge of fourth WE# (or CE#) pulse for Pro-
gram operation. For Sector-, Block-, or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 12 for Data# Polling (DQ
7
) timing
diagram and Figure 26 for a flowchart.
Data
Data
Data
1
DQ7#
Toggle
N/A
0
T2.1 1342
Note:
DQ
7,
DQ
6,
and DQ
2
require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
4
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Data Protection
The SST36VF160xG provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST36VF1601G and SST36VF1602G provide hard-
ware block protection which protects the outermost 8
KWord in the smaller bank. The block is protected when
WP# is held low. See Figures 2, 3, 4, and 5 for Block-Pro-
tection location.
Block protection is disabled by driving WP# high. This
allows data to be erased or programmed into the protected
sectors. WP# must be held high prior to issuing the Write
command and remain stable until after the entire Write
operation has completed. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate and
return to Read mode (see). When no internal Program/
Erase operation is in progress, a minimum period of T
RHR
is required after RST# is driven high before a valid Read
can take place. See Figures 22 and 21 for more informa-
tion.
The interrupted Erase or Program operation must be re-ini-
tiated after the device resumes normal operation mode to
ensure data integrity.
Software Data Protection (SDP)
The SST36VF160xG devices implement the JEDEC
approved Software Data Protection (SDP) scheme for all
data alteration operations, such as Program and Erase.
These devices are shipped with the Software Data Protec-
tion permanently enabled. See Table 6 for the specific soft-
ware command codes.
All Program operations require the inclusion of the three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations. SDP for Erase opera-
tions is similar to Program, but a six-byte load sequence is
required for Erase operations.
During SDP command sequence, invalid commands will
abort the device to read mode within T
RC.
The contents of
DQ
15
-DQ
8
can be V
IL
or V
IH
, but no other value, during any
SDP command sequence.
Common Flash Memory Interface (CFI)
These devices contain Common Flash Memory Interface
(CFI) information that describes the characteristics of the
device. In order to enter the CFI Query mode, the system
must write a three-byte sequence, using the CFI Query
command, to address BKx555H in the last byte sequence.
The system can also use the one-byte sequence with
address BKx55H and Data Bus 98H to enter this mode.
See Figure 18 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 7
through 9.
The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Security ID
The SST36VF160xG offer a 136-word Security ID space.
The Secure ID space is divided into two segments — one
128-bit, factory-programmed, segment and one 256-Byte,
user programmed segment. The first segment is pro-
grammed and locked at SST and contains a 128 bit Unique
ID which uniquely identifies the device. The user segment is
left un-programmed for the customer to program as desired.
The user segment of the Security ID can be programmed
using the Security ID Program command. End-of-Write sta-
tus is checked by reading the toggle bits. Data# Polling is
not used for Security ID End-of-Write detection.
Once the programming is complete, lock the Sec ID by
issuing the User Sec ID Program Lock-Out command.
Locking the Sec ID disables any corruption of this space.
Note that regardless of whether or not the Sec ID is locked,
the Sec ID segments can not be erased.
The Secure ID space can be queried by executing a three-
byte command sequence with Query Sec ID command
(88H) at address 555H in the last byte sequence. See Fig-
ure 20 for timing diagram. To exit this mode, the Exit Sec ID
command should be executed. Refer to Table 6 for more
details.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
5
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