L21C11
DEVICES INCORPORATED
8-bit Variable Length Shift Register
L21C11
DEVICES INCORPORATED
8-bit Variable Length Shift Register
DESCRIPTION
The
L21C11
is a high-speed, low
power CMOS variable length shift
register. It consists of a single 8-bit
wide, adjustable length shift regis-
ter. The shift register can be pro-
grammed to any length from 1 to 16
stages inclusive. The length of the
shift register is determined by the
Length Code (L
3-0
) as shown in
Table 1.
The Length Code (L
3-0
) controls the
number of delay stages applied to the
D
7-0
inputs as shown in Table 1.
When the Length Code is 0, the input
is delayed by 1 clock period. When
the Length Code is 1, the delay is 2
clock periods, and so forth. The
Length Code inputs are latched on the
rising edge of CLK. The Length Code
value may be changed at any time
without affecting the contents of
registers R1 through R15.
FEATURES
u
Variable Length 8-bit Wide Shift
Register
u
Selectable Delay Length from 1 to
16 Stages
u
Low Power CMOS Technology
u
Replaces TRW/Raytheon TMC2111
u
Load, Shift, and Hold Instructions
u
Separate Data In and Data Out Pins
u
DECC SMD No. 5962-96793
u
Available 100% Screened to
MIL-STD-883, Class B
u
Package Styles Available:
• 24-pin Plastic DIP
• 24-pin Ceramic DIP
• 28-pin Plastic LCC, J-Lead
• 28-pin Ceramic LCC
O
REGISTER R13
1
L21C11 B
LOCK
D
IAGRAM
REGISTER R14
REGISTER R15
LE
REGISTER R16
R15
R14
R13
The data input is applied to a chain
of registers which are clocked on the
rising edge of the CLK input. These
registers are numbered R1 through
R15. A multiplexer serves to route
the contents of any register, R1
through R15, or the data input, D
7-0
,
to the output register, denoted R16.
Note that the minimum-length path
from data input to output is through
R16, consisting of a single stage of
delay.
REGISTER R1
REGISTER R2
D
7-0
MUX
8
BS
REGISTER R3
TE
R3
R2
R1
8
Y
7-0
O
L
3-0
CLK
4
TO ALL REGISTERS
L REGISTER
Pipeline Registers
03/04/99–LDS.21C11-E
L21C11
DEVICES INCORPORATED
8-bit Variable Length Shift Register
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damag-
sources of
I
OH
and
I
OL
respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Never- used. Parasitic capacitance is 30 pF
theless, conventional precautions minimum, and may be distributed.
should be observed during storage,
handling, and use of these circuits in This device has high-speed outputs ca-
order to avoid exposure to excessive pable of large instantaneous current
electrical stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
3. This device provides hard clamping the testing of this device. The following
of transient undershoot and overshoot. measures are recommended:
Input levels below ground or above
V
CC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
V
CC
+ 0.6 V. The device can withstand installed between
V
CC
and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device
V
CC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values be-
yond those indicated in the Operating
Conditions table is not implied. Expo-
sure to maximum rating conditions for
extended periods may affect reliability.
11. For the
t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the
t
DIS
test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
TE
DUT
S1
C
L
I
OH
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
I
OL
V
TH
LE
Z
Z
F
IGURE
B. T
HRESHOLD
L
EVELS
t
ENA
1.5 V
1.5 V
t
DIS
OE
0
3.5V Vth
1.5 V
O
4
4. Actual test conditions may vary b. Ground and
V
CC
supply planes
from those designated but operation is must be brought directly to the DUT
guaranteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated compensate for inductive ground and
V
CC
by:
noise to maintain required DUT input
NCV
2
F
levels relative to the DUT ground pin.
where
V
OL
*
0.2 V
0
1
Z
Z
1.5 V
V
OH
*
0.2 V
1
0V Vth
V
OL
* Measured V
OL
with I
OH
= –10mA and I
OL
= 10mA
V
OH
* Measured V
OH
with I
OH
= –10mA and I
OL
= 10mA
O
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
BS
4
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses
from the internal circuitry are specified
from the point of view of the device.
Output delay, for example, is specified
as a maximum since worst-case opera-
tion of any device always provides data
within that time.
Pipeline Registers
03/04/99–LDS.21C11-E
FPGA/CPLD
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