converter with an on-board reference and output amplifier. It is
manufactured on Analog Devices’ BiMOS II process. This pro-
cess allows the fabrication of low power CMOS logic functions
on the same chip as high precision bipolar linear circuitry. The
AD669 chip includes current switches, decoding logic, an output
amplifier, a buried Zener reference and double-buffered latches.
The AD669’s architecture insures 15-bit monotonicity over
temperature. Integral nonlinearity is maintained at
±
0.003%,
while differential nonlinearity is
±
0.003% max. The on-chip
output amplifier provides a voltage output settling time of 10
µs
to within 1/2 LSB for a full-scale step.
Data is loaded into the AD669 in a parallel 16-bit format. The
double-buffered latch structure eliminates data skew errors and
provides for simultaneous updating of DACs in a multi-DAC
system. Three TTL/LSTTL/5 V CMOS compatible signals con-
trol the latches:
CS, L1
and LDAC.
The output range of the AD669 is pin programmable and can
be set to provide a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V.
The AD669 is available in seven grades: AN and BN versions
are specified from –40°C to +85°C and are packaged in a 28-pin
plastic DIP. The AR and BR versions are specified for –40°C to
+85°C operation and are packaged in a 28-pin SOIC. The SQ
version is specified from –55°C to +125°C and is packaged in a
hermetic 28-pin cerdip package. The AD669 is also available
compliant to MIL-STD-883. Refer to the AD669/883B data
sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.
1. The AD669 is a complete voltage output 16-bit DAC with
voltage reference and digital latches on a single IC chip.
2. The internal buried Zener reference is laser trimmed to
10.000 volts with a
±
0.2% maximum error. The reference
voltage is also available for external applications.
3. The AD669 is both dc and ac specified. DC specs include
±
1 LSB INL error and
±
1 LSB DNL error. AC specs include
0.009% THD+ N and 83 dB SNR. The ac specifications
make the AD669 suitable for signal generation applications.
4. The double-buffered latches on the AD669 eliminate data
skew errors while allowing simultaneous updating of DACs in
multi-DAC systems.
5. The output range is a pin-programmable unipolar 0 V to
+10 V or bipolar –10 V to +10 V output. No external compo-
nents are necessary to set the desired output range.
6. The AD669 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD669/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD669–SPECIFICATIONS
(@ T = +25 C, V
A
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V, unless otherwise noted)
AD669AQ/SQ
Min
Typ
Max
16
5.5
0.8
10
10
2
4
2
4
*
*
*
*
*
*
*
*
*
*
14
0.15
25
5
5
15
12
0.10
15
5
3
15
10
*
*
*
*
1000
*
*
*
*
*
*
*
*
*
*
15
*
*
*
*
*
*
*
*
*
15
0.10
15
2.5
3
10
5
*
*
*
15
AD669BN/BQ/BR
Min
Typ
Max
16
*
*
*
*
*
*
1
2
1
2
Units
Bits
Volts
Volts
µA
µA
LSB
LSB
LSB
LSB
Bits
% of FSR
ppm/°C
mV
ppm/°C
mV
ppm/°C
kΩ
kΩ
Volts
ppm/°C
mA
pF
mA
Model
RESOLUTION
DIGITAL INPUTS (T
MIN
to T
MAX
)
V
IH
(Logic “1” )
V
IL
(Logic “0” )
I
IH
(V
IH
= 5.5 V)
I
IL
(V
IL
= 0 V)
TRANSFER FUNCTION CHARACTERISTICS
1
Integral Nonlinearity
T
MIN
to T
MAX
Differential Nonlinearity
T
MIN
to T
MAX
Monotonicity Over Temperature
Gain Error
2, 5
Gain Drift
2
(T
MIN
to T
MAX
)
Unipolar Offset
Unipolar Offset Drift (T
MIN
to T
MAX
)
Bipolar Zero Error
Bipolar Zero Error Drift (T
MIN
to T
MAX
)
REFERENCE INPUT
Input Resistance
Bipolar Offset Input Resistance
REFERENCE OUTPUT
Voltage
Drift
External Current
3
Capacitive Load
Short Circuit Current
OUTPUT CHARACTERISTICS
Output Voltage Range
Unipolar Configuration
Bipolar Configuration
Output Current
Capacitive Load
Short Circuit Current
POWER SUPPLIES
Voltage
V
CC4
V
EE4
V
LL
Current (No Load)
I
CC
I
EE
I
LL
@ V
IH
, V
IL
= 5, 0 V
@ V
IH
, V
IL
= 2.4, 0.4 V
Power Supply Sensitivity
Power Dissipation (Static, No Load)
TEMPERATURE RANGE
Specified Performance (A, B)
Specified Performance (S)
AD669AN/AR
Min
Typ
Max
16
2.0
0
14
7
7
9.98
2
10
10
10.00
4
25
13
13
10.02
25
0
–10
5
25
+10
+10
1000
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Volts
Volts
mA
pF
mA
+13.5
–13.5
+4.5
+12
–12
0.3
3
1
365
–40
+16.5
–16.5
+5.5
+18
–18
2
7.5
3
625
+85
*
*
*
*
*
*
*
*
*
–40
–55
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–40
*
*
*
*
*
*
*
*
Volts
Volts
Volts
mA
mA
mA
mA
ppm/%
mW
°C
°C
+85
+125
+85
NOTES
1
For 16-bit resolution, 1 LSB = 0.0015% of FSR = 15 ppm of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR = 30 ppm of FSR. For 14-bit resolution
1 LSB = 0.006% of FSR = 60 ppm of FSR. FSR stands for Full-Scale Range and is 10 V for a 0 V to + 10 V span and 20 V for a –10 V to +10 V span.
2
Gain error and gain drift measured using the internal reference. Gain drift is primarily reference related. See the Using the AD669 with the AD688 Reference section
for further information.
3
External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD669.
4
Operation on
±
12 V supplies is possible using an external reference like the AD586 and reducing the output range. Refer to the Internal/External Reference Use section.
5
Measured with fixed 50
Ω
resistors. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). Refer to
the Analog Circuit Connections section.
*Same as AD669AN/AR specification.
Specifications subject to change without notice.
Specifications in
boldface
are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifica-
tions are guaranteed. Those shown in boldface are tested on all production units.
–2–
REV. A
AD669
AC PERFORMANCE CHARACTERISTICS
Parameter
Output Settling Time
(Time to
±
0.0008% FS
with 2 kΩ, 1000 pF Load)
Limit
13
8
10
6
8
2.5
0.009
0.07
7.0
83
15
2
120
125
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
T
MIN
≤
T
A
≤
T
MAX
, V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V except where noted.)
Units
µs
max
µs
typ
µs
typ
µs
typ
µs
typ
µs
typ
% max
% max
% max
dB min
nV-s typ
nV-s typ
nV/√Hz typ
nV/√Hz typ
Test Conditions/Comments
20 V Step, T
A
= +25°C
20 V Step, T
A
= +25°C
20 V Step, T
MIN
≤
T
A
≤
T
MAX
10 V Step, T
A
= +25°C
10 V Step, T
MIN
≤
T
A
≤
T
MAX
1 LSB Step, T
MIN
≤
T
A
≤
T
MAX
0 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
–20 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
–60 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
T
A
= +25°C
DAC Alternately Loaded with 8000H and 7FFFH
DAC Alternately Loaded with 0000H and FFFFH;
CS
High
Measured at V
OUT
, 20 V Span; Excludes Reference
Measured at REF OUT
Total Harmonic Distortion + Noise
A, B, S Grade
A, B, S Grade
A, B, S Grade
Signal-to-Noise Ratio
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Output Noise Voltage
Density (1 kHz – 1 MHz)
Reference Noise
Specifications subject to change without notice.
Specifications in
boldface are
tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed. Those shown in boldface are tested on all production units.
TIMING CHARACTERISTICS
V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V, V
HI
= 2.4 V, V
LO
= 0.4 V
Limit
+25 C
40
40
30
10
90
40
130
40
120
10
Limit
–40 C to
+85 C
50
50
35
10
110
45
150
45
140
10
Limit
–55 C to
+125 C
55
55
40
15
120
45
165
45
150
15
CS
t
CS
t
L1
Parameter
(Figure la)
t
CS
t
LI
t
DS
t
DH
t
LH
t
LW
(Figure lb)
t
LOW
t
HIGH
t
DS
t
DH
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
L1
DATA
LDAC
t
DS
t
DH
t
LH
t
LW
Figure 1a. AD669 Level Triggered Timing Diagram
t
LOW
CS
AND/OR
L1,
LDAC
DATA
t
HIGH
Specifications subject to change without notice.
Specifications in
boldface
are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. Those shown in boldface are tested
on all production units.
t
DS
t
DH
TIE
CS
AND/OR
L1
TO GROUND OR TOGETHER WITH LDAC
Figure 1b. AD669 Edge Triggered Timing Diagram
REV. A
–3–
AD669
ESD SENSITIVITY
The AD669 features input protection circuitry consisting of large transistors and polysilicon series
resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy pulses
(Charged Device Model). Per Method 3015.2 of MIL-STD-883: C, the AD669 has been classified
as a Class 2 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
ABSOLUTE MAXIMUM RATINGS
*
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
V
EE
V
CC
V
LL
DGND
L1
CS
DB15
DB14
DB13
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
REF OUT
REF IN
SPAN/BIP
OFFSET
V
OUT
AGND
LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
V
CC
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17.0 V
V
EE
to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17.0 V
V
LL
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
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