Le9662
Dual Subscriber Line Interface Circuit
miSLIC
TM
Series
Product Brief
Features
•
•
•
Economical, fifth-generation line interface
solution for VoIP processors and SoCs
Dual Channel Architecture
Single port 4-wire interface control (ZSI)
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-
-
•
•
Compatible with numerous VoIP processors and
SoC solutions
Less expensive isolation than multi-port control
Simplifies board routing
Document ID# 147600
Version 2
October 2013
Ordering Information
Device OPN
Le9662WQCT
Le9662WQC
Device Type
Package
Packing
SLIC, BBABS/FBABS 56-pin QFN Tape&Reel
SLIC, BBABS/FBABS 56-pin QFN Tray
These Green packages meet RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
Description
The miSLIC
TM
Line Circuits together with
processor or SoC, provides an economical
solution for derived voice applications. The
devices are controlled by a VoIP processor
through a simple, single serial interface.
a VoIP
turn-key
miSLIC
or SoC
VoicePath SDK and VP-API-II Software
available to implement FXS functions
VeriVoice Professional Test Suite Software
•
Comprehensive subscriber loop testing,
including
Telcordia GR-909-CORE / TIA-1063
diagnostic testing
Industry leading advanced test software
Facilitates factory testing and calibration of
assembled boards
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•
•
•
VeriVoice Manufacturing Test Package (VVMT)
The dual channel Le9662 miSLIC device uses energy
efficient shared power supply topologies for reduced BOM
cost. The Le9662 can be configured for patent-pending
shared Buck-Boost Automatic Battery Switching (BBABS)
or for shared Flyback ABS (FBABS) operation. Ringing
and system power management are supported to limit the
peak power requirements of each telephone line FXS
port. The dual channel Le9662 features wideband clarity
and complete BORSCHT functionality.
Manufacturing self test and subscriber line diagnostics
are available features. All AC, DC, and power parameters
are programmable making the Le9662 device suitable for
any short loop application requiring SLIC functionality.
Low cost, Energy Efficient Shared Switching
Regulator Architectures
-
-
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Dual Output power supplies
Integrated battery switches
Up to 70 V
RMS
open circuit ringing with
5 REN load
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•
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Low cost, 2-Layer PCB Reference Designs
Complete Wideband BORSCHT functionality
Worldwide Programmability
Per channel Narrowband or Wideband
operation
Applications
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•
•
•
DSL Residential Gateways and Integrated
Access Devices (IADs)
Cable Embedded Multimedia Terminal
Adapters (eMTAs)
PON Single Family Units (SFU)
Fiber-to-the-premise (FTTX) solutions
Figure 1 - Le9662 Block Diagram
1
© 2013 Microsemi Corporation. All Rights Reserved.
Le9662
Selected Electrical Specifications
Description
Ambient Temperature, under Bias
Digital and Analog Supply Voltages
Operating Limits:
BBABS operation
VBH
VBL
FBABS operation
VBH (both lines active VBL), VBL < |-50| V
VBH (all other states)
VBL (in active states)
BBABS operation
FBABS operation
BBABS operation
FBABS operation
ILA
V
RING
R
L
P
D(max)
θ
JA
5REN
200 to 3400 Hz
1 kHz
T
A
= 85°C
T
A
DVDD, AVDD
Symbol
Test Conditions
Min
-40
3.135
3.3
Typ
Product Brief
Max
+85
3.465
Unit
°C
V
DC
-(VSW + (2 * |VBL|)
−
2V)
-40 V
DC
to -25 V
DC
V
DC
Off-Hook
Off-Hook
-150 V
DC
to -(VOC + 7.0) V
DC
-120 V
DC
to -(VOC + 7.0) V
DC
VBH to -20 V
DC
18
18
25
25
50
30
58
2
27
30
45
60
70
mA
V
RMS
dB
dB
W
°C/W
Line Current:
Ringing Voltage:
Two-Wire Return Loss
Longitudinal Balance
Device Power Dissipation, Continuous
Junction to Ambient Thermal Resistance
Device Power Consumption (Typical)
Shutdown
Disconnect
Low Power Idle Mode
Idle
Active
1 line Active, 1 line Ringing
Symbol
Test Conditions
Switchers off
On-Hook
BBABS
5
25
47
99
520
1523
FBABS
5
25
52
116
658
1506
Power
Unit
P
D
Per
Channel
On-Hook
Off-Hook, 300
Ω,
ILA = 25 mA
50 V
RMS
, 5REN
mW
Both
Channels
Device Pinout
RINGD1
RINGD2
TIPD1
TIPD2
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VBL1
VBL2
VBH
Package Drawings
RSN1
AVDD
RTV1
VREF
IHL1
TAC1
RAC1
TDC1
RDC1
LFC1
SWVSY
SWCMPY
SWISY
I/O2
1
/ VS1
1
2
3
4
5
6
7
8
9
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
41
40
39
38
37
RSN2
AVDD
RTV2
IREF
IHL2
TAC2
RAC2
TDC2
RDC2
LFC2
SWVSZ
SWCMPZ
SWISZ
I/O2
2
/ VS2
Exposed Ground Pad
36
35
34
33
32
31
30
10
11
12
13
14
29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VDDSW
SWOUTY
ZCLK
I/O1
1
SWOUTZ
ZMOSI
ZMISO
DVDD
DVDD1V2
Related Collateral
•
•
Le9662 Shared Battery Dual miSLIC
TM
Line Circuit Preliminary Data Sheet,
Document ID# 146852
Le9672 Tracking Battery Dual miSLIC
TM
Line Circuit Preliminary Data Sheet,
Document ID# 146853
VDDHPI
ZSYNC
RSVD
I/O1
2
RST
2
© 2013 Microsemi Corporation. All Rights Reserved.
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