A range of dc rated multi-layer chip capacitors from
0.47pF to 22µF and in case sizes 0603 to 8060 in
C0G/NP0 and X7R dielectrics. Suitable for all general
purpose and high reliability applications where package
size and reliability are important. All are manufactured
using Syfer’s unique wet process and incorporate
precious metal electrodes.
Dissipation Factor
Ageing Rate
Range Dimensions – Standard MLCC Ranges
Length
(L1)
mm/inches
1.6 ± 0.2
0.063 ± 0.008
2.0 ± 0.3
0.08 ± 0.012
3.2 ± 0.3
0.126 ± 0.012
3.2 ± 0.3
0.126 ± 0.012
4.5 ± 0.35
0.18 ± 0.014
4.5 ± 0.35
0.18 ± 0.014
4.5 ± 0.35
0.18 ± 0.014
5.7 ± 0.4
0.225 ± 0.016
5.7 ± 0.4
0.225 ± 0.016
9.2 ± 0.5
0.36 ± 0.02
14.0 ± 0.5
0.55 ± 0.02
20.3 ± 0.5
0.8 ± 0.02
Width
(W)
mm/inches
0.8 ± 0.2
0.031 ± 0.008
1.25 ± 0.2
0.05 ± 0.008
1.6 ± 0.2
0.063 ± 0.008
2.5 ± 0.3
0.1 ± 0.012
2.0 ± 0.3
0.08 ± 0.012
3.2 ± 0.3
0.126 ± 0.012
6.30 ± 0.4
0.25 ± 0.016
5.0 ± 0.4
0.197 ± 0.016
6.3 ± 0.4
0.25 ± 0.016
10.16 ± 0.5
0.4 ± 0.02
12.7 ± 0.5
0.5 ± 0.02
15.24 ± 0.5
0.6 ± 0.02
Max. Thickness
(T)
mm/inches
0.8
0.013
1.3
0.051
1.6
0.063
2.0
0.08
2.0
0.08
2.5
0.1
2.5
0.1
4.2
0.16
4.2
0.16
2.5
0.1
4.2
0.16
2.5
0.1
Termination Band
(L2)
mm/inches
min
0.10
0.004
0.13
0.005
0.25
0.01
0.25
0.01
0.25
0.01
0.25
0.01
0.25
0.01
0.25
0.01
0.25
0.01
0.5
0.02
0.5
0.02
0.5
0.02
max
0.40
0.015
0.75
0.03
0.75
0.03
0.75
0.03
1.0
0.04
1.0
0.04
1.0
0.04
1.0
0.04
1.0
0.04
1.5
0.06
1.5
0.06
1.5
0.06
Size
0603
0805
1206
1210
1808
1812
1825
2220
2225
3640
5550
8060
Custom chip sizes not included in the table, but larger than 2225, can be considered with minimum tooling charges. Please refer specific requests direct to the sales office.
Max thickness relates to standard components and actual thickness may be considerably less. Thicker parts, or components with reduced maximum thickness, can be considered by request – please refer
//This is an example of debounce in the book module key_debounce_3 (clk_10m, rst_n, key_in, key_out); input clk_10m,rst_n,key_in; output key_out; //------------- -------------------------- reg key_rst...
[i=s]This post was last edited by 时光1111 on 2019-10-31 13:46[/i]When answering, please comment promptly
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FPGA/CPLD
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