Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 25, 2012
fido1100
®
Data Sheet
32-Bit Real-Time Communications Controller
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Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 25, 2012
Copyright
2012 by Innovasic, Inc.
Published by Innovasic, Inc.
5635 Jefferson St. NE, Suite A, Albuquerque, New Mexico 87109 USA
fido
®
, fido1100
®
, and SPIDER are trademarks of Innovasic, Inc.
I
2
C™ Bus is a trademark of Philips Electronics N.V.
Motorola
is a registered trademark of Motorola, Inc.
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Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 25, 2012
TABLE OF CONTENTS
List of Figures ..................................................................................................................................5
List of Tables ...................................................................................................................................6
1.
Overview.................................................................................................................................7
2.
Features ...................................................................................................................................9
2.1 Core CPU ....................................................................................................................10
2.2 JTAG ...........................................................................................................................10
2.3 Internal Memory and Memory Management ..............................................................11
2.4 External Bus Interface .................................................................................................12
2.5 PMU/UIC/CPU DMA .................................................................................................12
2.6 Internal Peripherals .....................................................................................................13
2.6.1 Timer Counter Units (TCU) ...........................................................................13
2.6.2 Analog-to-Digital Converter (ADC)...............................................................14
2.6.3 Timers .............................................................................................................14
2.7 Power Control .............................................................................................................14
3.
Libraries and Support Tools .................................................................................................15
4.
Packaging, Pin Descriptions, and Physical Dimensions .......................................................16
4.1 PQFP Package .............................................................................................................17
4.1.1 PQFP Pinout ...................................................................................................17
4.1.2 PQFP Physical Dimensions ............................................................................24
4.2 BGA 10- by 10-mm Package ......................................................................................25
4.2.1 BGA 10- by 10-mm Pinout.............................................................................25
4.2.2 BGA 10- by 10-mm Physical Package Dimensions .......................................33
4.3 BGA 15- by 15-mm Package ......................................................................................34
4.3.1 BGA 15- by 15-mm Pinout.............................................................................34
4.3.2 BGA 15- by 15-mm Physical Package Dimensions .......................................42
4.3.3 BGA 15- by 15-mm Signal Routing ...............................................................43
4.4 Power and Ground Signals ..........................................................................................45
5.
Electrical Characteristics ......................................................................................................47
6.
Thermal Characteristics ........................................................................................................49
7.
Reset .....................................................................................................................................52
7.1 Overview .....................................................................................................................52
7.2 Signal Considerations and Reset Timing ....................................................................52
7.3 Clock Signals...............................................................................................................54
7.4 Typical Clock Source Implementations ......................................................................54
7.4.1 Normal or Driven Clock Source .....................................................................54
7.4.2 Using an External Crystal ...............................................................................54
7.5 Off-Chip Component Value ........................................................................................56
8.
Signals...................................................................................................................................57
8.1 External Bus Operation ...............................................................................................57
8.1.1 Overview.........................................................................................................57
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Flexible Input Deterministic Output (fido
®
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32-Bit Real-Time Communications Controller
Data Sheet
April 25, 2012
9.
10.
11.
12.
13.
14.
8.2 General Setup and Hold Timing..................................................................................57
8.3 External Bus Timing ...................................................................................................58
Setup and Hold Timing .........................................................................................................59
9.1.1 External Bus Timing for a 32-Bit Transfer (without RDY_N) ......................61
9.1.2 External Bus Timing for a 32-Bit Transfer (with RDY_N) ...........................62
9.1.3 External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N) ................64
9.1.4 External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) .....................65
9.2 SDRAM Timing ..........................................................................................................66
9.2.1 SDRAM CAS Timing.....................................................................................66
9.2.2 SDRAM Row Activation Timing ...................................................................67
9.2.3 SDRAM Read Operation Timing ...................................................................69
9.2.4 SDRAM Read Burst Timing ..........................................................................69
9.2.5 SDRAM Write Operation, Write Burst, Write-to-Write, and Write-to-
Precharge Timing............................................................................................70
JTAG.....................................................................................................................................74
10.1 JTAG Scan Chain Debug Functionality ......................................................................75
Ordering Information ............................................................................................................77
Errata.....................................................................................................................................78
12.1 Summary .....................................................................................................................78
12.2 Detail ...........................................................................................................................78
Revision History ...................................................................................................................82
For Additional Information...................................................................................................83
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Flexible Input Deterministic Output (fido
®
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32-Bit Real-Time Communications Controller
Data Sheet
April 25, 2012
LIST OF FIGURES
Figure 1. Block Diagram for the fido1100......................................................................................8
Figure 2. PQFP Package Diagram ................................................................................................17
Figure 3. PQFP Physical Package Dimensions.............................................................................24
Figure 4. BGA 10- by 10-mm Package Diagram .........................................................................26
Figure 5. BGA 10- by 10-mm Physical Package Dimensions ......................................................33
Figure 6. BGA 15- by 15-mm Package Diagram .........................................................................35
Figure 7. BGA 15- by 15-mm Physical Package Dimensions ......................................................42
Figure 8. BGA 15- by 15-mm Signal Routing..............................................................................44
Figure 9. Thermal Performance of PQFP/BGA Under Forced Convection .................................50
Figure 10. Reset Timing ...............................................................................................................53
Figure 11. Extended Reset Timing ...............................................................................................53
Figure 12. Driven Clock Source ...................................................................................................55
Figure 13. Crystal Oscillator Third Overtone Off-Chip Components .........................................55
Figure 14. Crystal Oscillator Fundamental Overtone Off-Chip Components ..............................55
Figure 15. Propagation Delay .......................................................................................................59
Figure 16. Setup Time...................................................................................................................59
Figure 17. Hold Time ....................................................................................................................60
Figure 18. Recovery Time ............................................................................................................60
Figure 19. Removal Time .............................................................................................................60
Figure 20. Minimum Pulse Width ................................................................................................61
Figure 21. External Bus Timing for a Single, 32-Bit Cycle (without RDY_N) ...........................62
Figure 22. External Bus Timing for a 32-Bit Transfer (with RDY_N) ........................................63
Figure 23. External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N).............................64
Figure 24. External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) ..................................65
Figure 25. SDRAM CAS Timing .................................................................................................67
Figure 25. Specific Row Activation Timing .................................................................................68
Figure 27. Meeting tRCD (min) When 2 < tRCD (min)/tCK ≤ 3 ................................................68
Figure 28. SDRAM Read Operation Timing ................................................................................69
Figure 29. SDRAM Read Burst Timing .......................................................................................70
Figure 30. SDRAM Write Operation Timing ...............................................................................71
Figure 31. SDRAM Write Burst Timing ......................................................................................72
Figure 32. SDRAM Write-to-Write Timing .................................................................................72
Figure 33. SDRAM Write-to-Precharge Timing ..........................................................................73
Figure 34. JTAG State Machine ...................................................................................................74
Figure 35. JTAG Port Register Interface ......................................................................................75
Figure 36. Timing of JTAG Signals .............................................................................................75
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