SPP3481
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP3481 is the P-Channel logic enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits, and low in-line power loss are needed in a very
small outline surface mount package.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
-30V/-5.2A,R
DS(ON)
= 55mΩ@V
GS
=- 10V
-30V/-4.2A,R
DS(ON)
= 75mΩ@V
GS
=-4.5V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
TSOP-6P package design
PIN CONFIGURATION(TSOP-6P)
PART MARKING
2007/03/19
Ver.1
Page 1
SPP3481
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
4
5
6
ORDERING INFORMATION
Part Number
SPP3481ST6RG
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPP3481ST6RG : Tape Reel ; Pb – Free
Package
TSOP-6P
Part
Marking
81YW
Symbol
D
D
G
S
D
D
Description
Drain
Drain
Gate
Source
Drain
Drain
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
-30
±20
-5.2
-4.2
-20
-1.7
2.0
1.3
150
-55/150
90
Unit
V
V
A
A
A
W
℃
℃
℃
/W
2007/03/19
Ver.1
Page 2
SPP3481
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=-250uA
V
GS(th)
V
DS
=V
GS
,I
D
=-250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±20V
V
DS
=-24V,V
GS
=0V
V
DS
=-24V,V
GS
=0V
T
J
=55℃
V
DS
≦-5V,V
GS
=-10V
V
GS
=- 10V,I
D
=-5.2A
V
GS
=-4.5V,I
D
=-4.2A
V
DS
=-5.0V,I
D
=-4.0A
I
S
=-1.0A,V
GS
=0V
-30
-1.0
-3.0
±100
-1
-10
-10
0.042
0.058
10
-0.8
0.055
0.075
-1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=-15V,V
GS
=-10V
I
D
≡-4.0A
14
1.9
3.7
540
131
105
10
21
nC
V
DS
=-15V,V
GS
=0V
f=1MHz
pF
15
25
50
30
ns
V
DD
=-15V,R
L
=15Ω
I
D
≡-1.0A,V
GEN
=-10V
R
G
=6Ω
15
31
20
2007/03/19
Ver.1
Page 3
FPGA/CPLD
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