SPN2304
N-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPN2304 is the N-Channel logic enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits, and low in-line power loss are needed in a very
small outline surface mount package.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
30V/3.2A,R
DS(ON)
= 65mΩ@V
GS
=10V
30V/2.0A,R
DS(ON)
= 90mΩ@V
GS
=4.5V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-23-3L package design
PIN CONFIGURATION(SOT-23-3L)
PART MARKING
2007/02/ 02
Ver.4
Page 1
SPN2304
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
ORDERING INFORMATION
Part Number
SPN2304S23RG
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPN2304S23RG : Tape Reel ; Pb – Free
Package
SOT-23-3L
Part
Marking
04YW
Symbol
G
S
D
Description
Gate
Source
Drain
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
30
±20
3.2
2.6
10
1.25
1.25
0.8
150
-55/150
100
Unit
V
V
A
A
A
W
℃
℃
℃
/W
2007/02/ 02
Ver.4
Page 2
SPN2304
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=250uA
V
GS(th)
V
DS
=V
GS
,I
D
=250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±20V
V
DS
=30V,V
GS
=1.0V
V
DS
=30V,V
GS
=0.0V
T
J
=55℃
V
DS
≧4.5V,V
GS
=10V
V
DS
≧4.5V,V
GS
=4.5V
V
GS
= 10V,I
D
=3.2A
V
GS
=4.5V,I
D
=2.0A
V
DS
=4.5V,I
D
=2.5A
I
S
=1.25A,V
GS
=0V
30
1.0
3.0
±100
1
10
6
4
0.050
0.065
4.6
0.82
0.065
0.090
1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=15V
GS
=10V
I
D
≡2.5
4.5
0.8
1.0
240
110
17
8
10
nC
V
DS
=15V
GS
=0V
f=1MHz
pF
20
30
35
20
ns
V
DD
=15R
L
=15
I
D
≡1.0A,V
GEN
=10
R
G
=6Ω
12
17
8
2007/02/ 02
Ver.4
Page 3
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