PCA6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
with interrupt output, reset, and configuration registers
Rev. 2. — 10 January 2013
Product data sheet
1. General description
The PCA6416A is a 16-bit general purpose I/O expander that provides remote I/O
expansion for most microcontroller families via the I
2
C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage
level to I/O devices operating at a different (usually higher) voltage level. The PCA6416A
has built-in level shifting feature that makes these devices extremely flexible in mixed
signal environments where communication between incompatible I/O voltages is required.
Its wide V
DD
range of 1.65 V to 5.5 V on the dual power rail allows seamless
communications with next-generation low voltage microprocessors and microcontrollers
on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCA6416A: V
DD(I2C-bus)
and V
DD(P)
. V
DD(I2C-bus)
provides the supply voltage for the interface at the master side (for example, a
microcontroller) and the V
DD(P)
provides the supply for core circuits and Port P. The
bidirectional voltage level translation in the PCA6416A is provided through V
DD(I2C-bus)
.
V
DD(I2C-bus)
should be connected to the V
DD
of the external SCL/SDA lines. This indicates
the V
DD
level of the I
2
C-bus to the PCA6416A. The voltage level on Port P of the
PCA6416A is determined by the V
DD(P)
.
The PCA6416A register set consists of four pairs of 8-bit Configuration, Input, Output, and
Polarity Inversion registers.
At power-on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity Inversion register, saving external
logic gates.
The system master can reset the PCA6416A in the event of a time-out or other improper
operation by asserting a LOW in the RESET input. The power-on reset puts the registers
in their default state and initializes the I
2
C-bus/SMBus state machine. The RESET pin
causes the same reset/initialization to occur without depowering the part.
The PCA6416A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
NXP Semiconductors
PCA6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I
2
C-bus. Thus, the PCA6416A can
remain a simple slave device.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while
consuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I
2
C-bus address
and allow up to two devices to share the same I
2
C-bus or SMBus.
2. Features and benefits
I
2
C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Allows bidirectional voltage-level translation and GPIO expansion between:
1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
Low standby current consumption:
1.5
A
typical at 5 V V
DD
1.0
A
typical at 3.3 V V
DD
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
V
hys
= 0.18 V (typical) at 1.8 V
V
hys
= 0.25 V (typical) at 2.5 V
V
hys
= 0.33 V (typical) at 3.3 V
V
hys
= 0.5 V (typical) at 5 V
5 V tolerant I/O ports
Active LOW reset input (RESET)
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I
2
C-bus
Input/Output Configuration register
Polarity Inversion register
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Noise filter on SCL/SDA inputs
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD protection exceeds JESD 22
2000 V Human-Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP24, HWQFN24, VFBGA24
PCA6416A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 January 2013
2 of 42
NXP Semiconductors
PCA6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
3. Ordering information
Table 1.
Ordering information
Topside
marking
416A
416A
Package
Name
VFBGA24
Description
plastic very thin fine-pitch ball grid array package; 24 balls;
body 3
3
0.85 mm
Version
SOT1199-1
SOT994-1
SOT355-1
Type number
PCA6416AEV
PCA6416AHF
PCA6416APW
HWQFN24 plastic thermal enhanced very very thin quad flat package;
no leads; 24 terminals; body 4
4
0.75 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
PCA6416A TSSOP24
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA6416AEVJ
PCA6416AHF,128
PCA6416APW,118
Package
VFBGA24
HWQFN24
TSSOP24
Packing method
Reel pack, SMD,
13-inch
Reel pack, SMD,
13-inch, turned
Reel pack, SMD,
13-inch
Minimum
order quantity
6000
6000
2500
Temperature
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCA6416AEV
PCA6416AHF
PCA6416APW
4. Block diagram
PCA6416A
INT
LP FILTER
INTERRUPT
LOGIC
ADDR
P0_0 to P0_7
P1_0 to P1_7
SCL
SDA
INPUT
FILTER
I
2
C-BUS
CONTROL
SHIFT
REGISTER
16 BITS
I/O
PORT
V
DD(I2C-bus)
V
DD(P)
RESET
V
SS
POWER-ON
RESET
write pulse
read pulse
002aaf537
All I/Os are set to inputs at reset.
Fig 1.
Block diagram (positive logic)
PCA6416A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 January 2013
3 of 42
NXP Semiconductors
PCA6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
5. Pinning information
5.1 Pinning
23 V
DD(I2C-bus)
24 RESET
20 SDA
V
DD(I2C-bus)
RESET
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
2
3
4
5
6
7
8
9
terminal 1
index area
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
1
2
3
4
5
6
22 SCL
21 ADDR
20 P1_7
19 P1_6
18 P1_5
17 P1_4
16 P1_3
15 P1_2
14 P1_1
13 P1_0
002aaf535
19 SCL
18 ADDR
17 P1_7
16 P1_6
15 P1_5
14 P1_4
13 P1_3
P1_2 12
4
SDA
002aaf536
PCA6416APW
PCA6416AHF
P1_0 10
P0_6
P0_7
V
SS
12
Transparent top view
The exposed center pad, if used, must be
connected only as a secondary ground or
must be left electrically open.
Fig 2.
Pin configuration for TSSOP24
PCA6416AEV
1
2
3
4
5
Fig 3.
Pin configuration for HWQFN24
ball A1
index area
A
B
A
B
D
C
E
D
002aaf786
1
P0_0
P0_2
P0_3
P0_5
P0_6
2
RESET
V
SS
3
P0_7 11
P1_1 11
7
8
9
P0_6 10
22 INT
INT
1
24 V
DD(P)
23 SDA
21 V
DD(P)
5
SCL
ADDR
P1_6
P1_5
P1_3
002aah370
C
INT
V
DD(I2C-bus)
V
DD(P)
P0_4
P0_7
V
SS
P0_1
P1_2
P1_0
P1_7
P1_4
P1_1
E
Transparent top view
An empty cell indicates no ball
is populated at that grid point.
Fig 4.
Pin configuration for VFBGA24
Fig 5.
Ball mapping for VFBGA24
(transparent top view)
PCA6416A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 January 2013
4 of 42
NXP Semiconductors
PCA6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
5.2 Pin description
Table 3.
Symbol
INT
V
DD(I2C-bus)
RESET
P0_0
[1]
P0_1
[1]
P0_2
[1]
P0_3
[1]
P0_4
[1]
P0_5
[1]
P0_6
[1]
P0_7
[1]
V
SS
P1_0
[2]
P1_1
[2]
P1_2
[2]
P1_3
[2]
P1_4
[2]
P1_5
[2]
P1_6
[2]
P1_7
[2]
ADDR
SCL
SDA
V
DD(P)
[1]
[2]
Pin description
Pin
TSSOP24 HWQFN24 VFBGA24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A3
B3
A2
A1
C3
B1
C1
C2
D1
E1
D2
E2
E3
E4
D3
E5
D4
D5
C5
C4
B5
A5
A4
B4
Interrupt output. Connect to V
DD(I2C-bus)
or V
DD(P)
through a pull-up
resistor.
Supply voltage of I
2
C-bus. Connect directly to the V
DD
of the external
I
2
C master. Provides voltage-level translation.
Active LOW reset input. Connect to V
DD(I2C-bus)
through a pull-up
resistor if no active connection is used.
Port 0 input/output 0.
Port 0 input/output 1.
Port 0 input/output 2.
Port 0 input/output 3.
Port 0 input/output 4.
Port 0 input/output 5.
Port 0 input/output 6.
Port 0 input/output 7.
Ground.
Port 1 input/output 0.
Port 1 input/output 1.
Port 1 input/output 2.
Port 1 input/output 3.
Port 1 input/output 4.
Port 1 input/output 5.
Port 1 input/output 6.
Port 1 input/output 7.
Address input. Connect directly to V
DD(P)
or ground.
Serial clock bus. Connect to V
DD(I2C-bus)
through a pull-up resistor.
Serial data bus. Connect to V
DD(I2C-bus)
through a pull-up resistor.
Supply voltage of PCA6416A for Port P.
Description
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-on, all I/O are configured as input.
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-on, all I/O are configured as input.
PCA6416A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 January 2013
5 of 42
京公网安备 11010802033920号
EEWORLD
