SHARC+ Dual-Core
DSP with ARM Cortex-A5
ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
SYSTEM FEATURES
Dual-enhanced SHARC+ high performance floating-point
cores
Up to 500 MHz per SHARC+ core
Up to 3 Mb (384 kB) L1 SRAM memory per core with parity
(optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short word, word, long word addressed
ARM Cortex-A5 core
500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
32 kB L1 instruction cache with parity/32 kB L1 data cache
with parity
256 kB L2 cache with parity
Powerful DMA system
On-chip memory protection
Integrated safety features
SYSTEM CONTROL
SECURITY AND PROTECTION
SYSTEM PROTECTION (SPU)
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
FAULT MANAGEMENT
ARM® TrustZone® SECURITY
DUAL CRC
WATCHDOGS
OTP MEMORY
THERMAL MONITOR UNIT (TMU)
PROGRAM FLOW
SYS EVENT CORE 0 (GIC)
SYS EVENT CORES 1-2 (SEC)
TRIGGER ROUTING (TRU)
CLOCK, RESET, AND POWER
CLOCK GENERATION (CGU)
CLOCK DISTRIBUTION
UNIT (CDU)
RESET CONTROL (RCU)
POWER MANAGEMENT (DPM)
DEBUG UNIT
ARM® CoreSight
TM
WATCHPOINTS (SWU)
16
DATA
ADC CONTROL MODULE
(ACM)
2× CAN2.0
L1 CACHE (PARITY)
32 kB L1 I-CACHE
32 kB L1 D-CACHE
L2 CACHE
256 kB (PARITY)
L1 SRAM (PARITY)
3 Mb (384 kB)
SRAM/CACHE
L1 SRAM (PARITY)
3 Mb (384 kB)
SRAM/CACHE
CORE 0
CORE 1
17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP,
RoHS compliant
Low system power across automotive temperature range
MEMORY
Large on-chip L2 SRAM with ECC protection, up to 1 MB
One L3 interface optimized for low system power, providing
16-bit interface to DDR3 (supporting 1.5 V capable DDR3L
devices), DDR2, or LPDDR1 SDRAM devices
ADDITIONAL FEATURES
Security and Protection
Cryptographic hardware accelerators
Fast secure boot with IP protection
Support for ARM TrustZone
Accelerators
FIR, IIR offload engines
Qualified for automotive applications
CORE 2
PERIPHERALS
SIGNAL ROUTING UNIT (SRU)
2× PRECISION CLOCK
GENERATORS
ASRC
4× PAIRS
1x DAI
FULL SPORT 1x PIN
0-3
BUFFER
20
S
S
1× S/PDIF Rx/Tx
3× I C
2× LINK PORTS
2× SPI + 1× QUAD SPI
3× UARTs
1× EPPI
6
2
SYSTEM CROSSBAR AND DMA SUBSYSTEM
8× TIMERS + 1× COUNTER
G
P
I
O
92–64
L3 MEMORY
INTERFACE
DDR3
DDR2
LPDDR1
SYSTEM
L2 MEMORY
SRAM
(ECC)
8 Mb (1 MB)
SYSTEM
ACCELERATION
DSP FUNCTIONS
(FIR, IIR)
ENCRYPTION/DECRYPTION
SD/SDIO/eMMC
MLB 3-PIN
1× EMAC
8x SHARC® FLAGS
1 USB 2.0 HS
MLB 6-PIN
6
HADC (8 CHAN, 12-BIT)
8–4
7
Figure 1. Processor Block Diagram
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Rev. B
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ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
TABLE OF CONTENTS
System Features ....................................................... 1
Memory ................................................................ 1
Additional Features .................................................. 1
Table Of Contents .................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
ARM Cortex-A5 Processor ...................................... 5
SHARC Processor ................................................. 6
SHARC+ Core Architecture .................................... 8
System Infrastructure ........................................... 10
System Memory Map ........................................... 11
Security Features ................................................ 13
Security Features Disclaimer .................................. 14
Safety Features ................................................... 14
Processor Peripherals ........................................... 15
System Acceleration ............................................ 19
System Design .................................................... 20
System Debug .................................................... 22
Development Tools ............................................. 22
Additional Information ........................................ 23
Related Signal Chains .......................................... 23
ADSP-SC57x/ADSP-2157x Detailed Signal
Descriptions ...................................................... 24
400-Ball CSP_BGA Signal Descriptions ....................... 28
GPIO Multiplexing for 400-Ball CSP_BGA Package ....... 35
176-Lead LQFP Signal Descriptions ........................... 38
GPIO Multiplexing for 176-Lead LQFP Package ............ 43
ADSP-SC57x/ADSP-2157x Designer Quick Reference .... 45
Specifications ........................................................ 56
Operating Conditions ........................................... 56
Electrical Characteristics ....................................... 60
HADC .............................................................. 64
TMU ................................................................ 64
Absolute Maximum Ratings ................................... 65
ESD Caution ...................................................... 65
Timing Specifications ........................................... 66
Output Drive Currents ....................................... 122
Test Conditions ................................................ 124
Environmental Conditions .................................. 126
ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball
Assignments .................................................... 127
Numerical by Ball Number .................................. 127
Alphabetical by Pin Name ................................... 130
Configuration of the 400-Ball CSP_BGA ................. 133
ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead
Assignments .................................................... 134
Numerical by Lead Number ................................. 134
Alphabetical by Pin Name ................................... 136
Configuration of the 176-Lead LQFP Lead
Configuration ................................................ 137
Outline Dimensions .............................................. 138
Surface-Mount Design ........................................ 139
Automotive Products ......................................... 140
Ordering Guide ................................................ 141
REVISION HISTORY
6/2018—Rev. A to Rev. B
Changes to
System Features ........................................ 1
Changes to
Additional Features ................................... 1
Changes to Table 2 and Table 3,
General Description ....... 3
Changes to
Operating Conditions .............................. 56
Deleted Package Information from
Specifications .......... 56
Changes to Table 27 and Table 28,
Clock Related Operating
Conditions ........................................................... 58
Changes to
Electrical Characteristics ........................... 60
Changes to Table 29, Table 32, and Table 33,
Total Internal
Power Dissipation .................................................. 62
Changes to Table 37,
HADC Timing Specifications ........ 64
Changes to
Program Trace Macrocell (PTM) Timing .... 120
Changes to
Test Conditions .................................... 124
Changes to
Automotive Products ............................. 140
Changes to
Ordering Guide .................................... 141
Rev. B | Page 2 of 142
| June 2018
ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
GENERAL DESCRIPTION
The ADSP-SC57x/ADSP-2157x processors are members of the
SHARC
®
family of products. The ADSP-SC57x processor is
based on the SHARC+
®
dual-core and the ARM
®
Cortex
®
-A5
core. The ADSP-SC57x/ADSP-2157x SHARC processors are
members of the single-instruction, multiple data (SIMD)
SHARC family of digital signal processors (DSPs) that feature
Analog Devices Super Harvard Architecture. These 32-bit/40-
bit/64-bit floating-point processors are optimized for high per-
formance audio/floating-point applications with large on-chip
static random-access memory (SRAM), multiple internal buses
that eliminate input/output (I/O) bottlenecks, and innovative
digital audio interfaces (DAI). New additions to the SHARC+
core include cache enhancements and branch prediction, while
maintaining instruction set compatibility to previous SHARC
products.
By integrating a set of industry leading system peripherals and
memory (see
Table 1, Table 2,
and
Table 3),
the ARM Cortex-
A5 and SHARC processor is the platform of choice for applica-
tions that require programmability similar to reduced
instruction set computing (RISC), multimedia support, and
leading edge signal processing in one integrated package. These
applications span a wide array of markets, including automo-
tive, professional audio, and industrial-based applications that
require high floating-point performance.
Table 2
provides comparison information for features that vary
across the standard processors.
Table 3
provides comparison information for features that vary
across the automotive processors.
Table 1. Common Product Features
Product Features
DAI (includes SRU)
Full SPORTs
S/PDIF receive/transmit
ASRCs
PCGs
Pin buffers
2
I C (TWI)
Quad-data bit SPI
Dual-data bit SPI
CAN2.0
UARTs
Enhanced PPI
Up to 16-bit on BGA
12-bit on LQFP
GP timer
GP counter
Watchdog timers
ADC control module
Hardware accelerators
FIR/IIR
Security cryptographic engine
Multichannel 12-bit ADC
ADSP-SC57x/ADSP-2157x
1
4
1
4
2
20
3
1
2
2
3
1
8
1
3
Yes
Yes
Yes
8-channel BGA; 4-channel LQFP
Rev. B | Page 3 of 142
| June 2018
ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
Table 2. Comparison of ADSP-SC57x/ADSP-2157x Processor Features
1
Processor Feature
ARM Cortex-A5 (MHz, Max)
ARM Core L1 Cache (I, D kB)
ARM Core L2 Cache (kB)
SHARC+ Core1 (MHz, Max)
SHARC+ Core2 (MHz, Max)
SHARC L1 SRAM (kB)
L2 SRAM (Shared) (MB)
DDR3/DDR2/LPDDR1 Controller
(16-bit)
USB 2.0 HS + PHY (Host/Device/OTG)
EMAC Std/AVB + Timer IEEE 1588
SDIO/eMMC
Link Ports
GPIO Ports
GPIO + DAI Pins
Package Options
N/A means not applicable.
System
Memory
ADSP-
SC570
450
32, 32
256
450
N/A
1 × 384
1
N/A
N/A
10/100
N/A
1
Port A to D
64 + 20
176-LQFP
ADSP-
SC571
500
32, 32
256
500
500
2 × 384
1
N/A
N/A
10/100
N/A
1
Port A to D
64 + 20
176-LQFP
ADSP-
SC572
450
32, 32
256
450
N/A
1 × 384
1
1
1
10/100/1000
1
2
Port A to F
92 + 20
400-BGA
ADSP-
SC573
500
32, 32
256
500
500
2 × 384
1
1
1
10/100/1000
1
2
Port A to F
92 + 20
400-BGA
ADSP-
21571
N/A
N/A
N/A
500
500
2 × 384
1
N/A
N/A
N/A
N/A
1
Port A to D
64 + 20
176-LQFP
ADSP-
21573
N/A
N/A
N/A
500
500
2 × 384
1
1
N/A
N/A
N/A
2
Port A to F
92 + 20
400-BGA
1
Table 3. Comparison of ADSP-SC57x/ADSP-2157x Processor Features for Automotive
1
Processor Feature
ARM Cortex-A5 (MHz, Max)
ARM Core L1 Cache (I, D kB)
ARM Core L2 Cache (kB)
SHARC+ Core1 (MHz, Max)
SHARC+ Core2 (MHz, Max)
SHARC L1 SRAM (kB)
L2 SRAM (Shared) (MB)
DDR3/DDR2/LPDDR1 Controller
(16-bit)
USB 2.0 HS + PHY (Host/Device/OTG)
EMAC Std/AVB + Timer IEEE 1588
SDIO/eMMC
MLB 3-Pin/6-Pin
Link Ports
GPIO Ports
GPIO + DAI Pins
Package Options
N/A means not applicable.
System
Memory
ADSP-
SC570W
450
32, 32
256
450
N/A
1 × 384
1
N/A
N/A
10/100
N/A
3-pin
1
Port A to D
64 + 20
176-LQFP
ADSP-
SC571W
500
32, 32
256
500
500
2 × 384
1
N/A
N/A
10/100
N/A
3-pin
1
Port A to D
64 + 20
176-LQFP
ADSP-
SC572W
450
32, 32
256
450
N/A
1 × 384
1
1
1
10/100/1000
1
6-pin/3-pin
2
Port A to F
92 + 20
400-BGA
ADSP-
SC573W
500
32, 32
256
500
500
2 × 384
1
1
1
10/100/1000
1
6-pin/3-pin
2
Port A to F
92 + 20
400-BGA
ADSP-
21571W
N/A
N/A
N/A
500
500
2 × 384
1
N/A
N/A
N/A
N/A
3-pin
1
Port A to D
64 + 20
176-LQFP
ADSP-
21573W
N/A
N/A
N/A
500
500
2 × 384
1
1
N/A
N/A
N/A
6-pin/3-pin
2
Port A to F
92 + 20
400-BGA
1
Rev. B | Page 4 of 142
| June 2018
ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
ARM CORTEX-A5 PROCESSOR
The ARM Cortex-A5 processor (see
Figure 2)
is a high perfor-
mance processor with the following features:
• Instruction cache unit (32 Kb) and data Level 1 (L1) cache
unit (32 Kb)
• In order pipeline with dynamic branch prediction
• ARM, Thumb, and ThumbEE instruction set support
• ARM TrustZone
®
security extensions
• Harvard L1 memory system with a memory management
unit (MMU)
• ARM v7 debug architecture
• Trace support through an embedded trace macrocell
(ETM) interface
• Extension—vector floating-point unit (IEEE754) with trap-
less execution
• Extension—media processing engine (MPE) with NEON
TM
technology
• Extension—Jazelle
®
hardware acceleration
EMBEDDED TRACE MACROCELL
(ETM) INTERFACE
CoreSight INTERFACE
TM
DEBUG
CP15
NEON
TM
MEDIA
PROCESSING
ENGINE
ARM Cortex-A5
PROCESSOR
®
®
DATA PROCESSING UNIT (DPU)
PREFETCH UNIT AND BRANCH PREDICTOR (PFU)
DATA MICRO TLB
INSTRUCTION MICRO TLB
DATA STORE
BUFFER (STB)
DATA CACHE
UNIT (DCU)
32 Kb
MAIN TRANSMISSION
LOOKINSIDE BUFFER (TLB)
INSTRUCTION CACHE
UNIT (ICU)
32 Kb
BUS INTERFACE UNIT (BIU)
ARM Cortex-A5 BUS MASTER PORT
®
®
GENERIC INTERRUPT
CONTROLLER
(PrimeCell
®
PL390)
L2 CACHE
CONTROLLER
(CoreLink
TM
PL310)
256 Kb
DATA MASTER PORTS
SHARC PROCESSORS
SYSTEM FABRIC
TO OTHER CORES
Figure 2. ARM Cortex-A5 Processor Block Diagram
Rev. B | Page 5 of 142
| June 2018
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