PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Features
•
•
•
•
•
•
•
•
•
•
Maximum operation frequency: 500 MHz
4 pair of differential LVPECL outputs
Selectable CLK
0
and CLK
1
inputs
CLK
0
, CLK
1
accept LVCMOS, LVTTL input level
Output Skew: 40ps (typical)
Propagation delay: 1.5ns (typical)
3.3V power supply
Additive jitter of 0.03ps (typical)
Operating Temperature: -40
o
C to 85
o
C
Packaging (Pb-free & Green available):
— 20-pin TSSOP (L)
Description
The PI6C48535-01B is a high-performance low-skew LVPECL
fanout buffer. PI6C48535-01B features two selectable single-ended
clock inputs and translates to four LVPECL outputs. The CLK
0
and CLK
1
inputs accept LVCMOS or LVTTL signals. The outputs
are synchronized with input clock during asynchronous assertion/
deassertion of CLK_EN pin. PI6C48535-01B is ideal for single-
ended LVTTL/LVCMOS to LVPECL translations. Typical clock
translation and distribution applications are data-communications
and telecommunications.
Block Diagram
CLK_EN
D
LE
CLK
0
CLK
1
0
1
Q
0
n
Q
0
Q
1
n
Q
1
CLK_SEL
Q
2
n
Q
2
Q
3
n
Q
3
Pin Configuration
Q
V
EE
CLK_EN
CLK_SEL
CLK
0
NC
CLK
1
NC
NC
NC
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q
0
NQ
0
V
CC
Q
1
NQ
1
Q
2
NQ
2
V
CC
Q
3
NQ
3
12-0258
1
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Pin Description
Name
V
EE
CLK_EN
CLK_SEL
CLK
0
CLK
1
NC
V
CC
Q
3
,
n
Q
3
Q
2
,
n
Q
2
Q
1
,
n
Q
1
Q
0
,
n
Q
0
Pin #
1
2
3
4
6
5, 7, 8, 9
10, 13,
18
11, 12
14, 15
16, 17
19, 20
P
O
O
O
O
Type
P
I_PU
I_PD
I_PD
I_PD
Connect to Negative power supply
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx
outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50KΩ
pull up.
Clock select input. When high, selects CLK
1
input. When low, selects CLK
0
input.
LVCMOS/LVTTL level with 50KΩ pull down.
LVCMOS / LVTTL clock input
LVCMOS / LVTTL clock input
No internal connection.
Connect to 3.3V.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Description
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up.
Pin Characteristics
Symbol
C
IN
R_pullup
R_pulldown
Parameter
Input Capacitance
Input Pullup Resistance
Input Pulldown Resistance
50
50
Conditions
Min.
Typ.
Max.
4
Units
pF
KΩ
Control Input Function Table
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK
0
CLK
1
CLK
0
CLK
1
Q
0
:Q
3
Diasbled: Low
Disabled: Low
Enabled
Enabled
Outputs
n
Q
0
:
n
Q
3
Diasbled: High
Disabled: High
Enabled
Enabled
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
12-0258
2
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Figure 1. CLK_EN Timing Diagram
Disabled
Enabled
CLK
0
CLK
1
CLK_EN
nQ0:nQ3
Q0:Q3
Clock Input Function Table
Inputs
CLK
0
or CLK
1
0
1
Q
0
:Q
3
LOW
HIGH
Outputs
n
Q
0
:
n
Q
3
HIGH
LOW
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
OUT
T
STG
Parameter
Supply voltage
Input voltage
Output voltage
Storage temperature
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
Min.
Typ.
Max.
4.6
V
CC
+0.5V
V
CC
+0.5V
150
V
o
C
Units
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci
fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Conditions
Symbol
V
CC
T
A
I
DD
Parameter
Power Supply Voltage
Ambient Temperature
Power Supply Current
All outputs unloaded
Conditions
Min.
3.0
-40
Typ.
3.3
Max.
3.6
85
130
Units
V
o
C
mA
12-0258
3
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
LVCMOS/LVTTL DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.0V to 3.6V unless otherwise stated below.)
Symbol
V
IH
V
IL
I
IH
I
IL
Input High
Voltage
Input Low
Voltage
Input High
Current
Input Low
Current
Parameter
CLK
0
, CLK
1
, CLK_EN,
CLK_SEL
CLK
0
, CLK
1
CLK_EN, CLK_SEL
CLK0, CLK1, CLK_SEL
CLK_EN
CLK
0
, CLK
1
, CLK_SEL
CLK_EN
V
IN
= V
CC
= 3.6V
V
IN
= V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
-10
-150
Conditions
Min.
2
-0.3
-0.3
Typ.
Max.
V
CC
+0.3
0.8
0.8
150
15
Units
V
V
V
uA
uA
uA
uA
LVPECL DC Characteristics
Symbol
V
OH
V
OL
Parameter
Output High Voltage
Output Low Voltage
Conditions
V
CC
= 3.3V
V
CC
= 3.3V
Min.
2.1
1.3
Typ.
Max.
2.6
1.8
Units
V
AC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.0V to 3.6V)
Symbol
f
max
t
Pd
T
sk(o)
t
r
/t
f
odc
J
add
Parameter
Output Frequency
Propagation Delay
Output-to-output Skew
Output Rise/Fall time
Output Duty Cycle
Additive Jitter
20% - 80%
48
30
1.5
40
150
52
Conditions
Min.
Typ.
Max.
500
Units
MHz
ns
ps
%
fs
Notes:
1. All parameters are measured with CMOS input of 266MHz unless stated otherwise
12-0258
4
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Configuration Test Load Board Termination for LVPECL
V
CC
Z
O
= 50Ω
TLA
Device
L = 0 ~ 10in
TLA
Z
O
= 50Ω
150Ω
150Ω
100Ω
12-0258
5
PI6C48535-01B
Rev A
09/25/2012
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