®
ISL6217A
Data Sheet
June 30, 2005
FN9107.3
Precision Multi-Phase Buck PWM
Controller for Intel, Mobile Voltage
Positioning IMVP-IV™ and IMVP-IV+™
The ISL6217A Multi-Phase Buck PWM controller IC, with
integrated half bridge gate drivers, provides a precision
voltage regulation system for advanced Pentium IV
microprocessors in notebook computers. Two-phase
operation eases the thermal management issues and load
demand of Intel’s latest high performance processors. This
control IC also features both input voltage feed-forward and
average current mode control for excellent dynamic
response, “Loss-less” current sensing using MOSFET
rDS(ON) and user-selectable switching frequencies from
250kHz to 1MHz per phase.
The ISL6217A includes a 6-bit digital-to-analog converter
(DAC) that dynamically adjusts the CORE PWM output
voltage from 0.700V to 1.708V in 16mV steps and conforms
to the Intel IMVP-IV™ and IMVP-IV+™ mobile VID
specification. The ISL6217A also has logic inputs to select
Active, Deep Sleep and Deeper Sleep modes of operation. A
precision reference, remote sensing and proprietary
architecture, with integrated, processor-mode, compensated
“Droop”, provide excellent static and dynamic CORE voltage
regulation.
To improve efficiency at light loading, the ISL6217A can be
configured to run in single phase PWM in ACTIVE, DEEP or
DEEPER SLEEP modes of operation. Also, in deep and
deeper sleep modes the ISL6217A will operate in diode
emulation.
Another feature of this IC controller is the PGOOD monitor
circuit that is held low until CORE voltage increases, during
its soft-start sequence, to within 12% of the “Boot” voltage.
This PGOOD signal is masked during VID changes. Output
overcurrent, overvoltage and undervoltage are monitored
and result in the converter latching off and PGOOD signal
being held low.
The overvoltage and undervoltage thresholds are 112% and
84% of the VID, Deep or Deeper Sleep setpoint,
respectively. Overcurrent protection features a 32 cycle
overcurrent shutdown. PGOOD, overvoltage, undervoltage
and overcurrent provide monitoring and protection for the
microprocessor and power system. The ISL6217A IC is
available in a 38 lead TSSOP.
Features
• Diode Emulation Functionality in deep and deeper sleep
modes for improved light load efficiency
• IMVP-IV™ and IMVP-IV+™ Compliant CORE Regulator
• Single and/or Two-phase Power Conversion
• “Loss-less” Current sensing for improved efficiency and
reduced board area
- Optional Discrete Precision Current Sense Resistor
• Internal Gate-Drive and Boot-Strap Diodes
• Precision CORE Voltage Regulation
- 0.8% system accuracy over temperature
• 6-Bit Microprocessor Voltage Identification Input
• Programmable “Droop” and CORE Voltage Slew Rate to
comply with IMVP-IV™ and IMVP-IV+™ specification
• Direct Interface with System Logic (STP_CPU# and
DPRSLPVR) for Deep and Deeper Sleep modes of
operation
• Easily Programmable voltage setpoints for Initial “Boot”,
Deep Sleep and Deeper Sleep Modes
• Excellent Dynamic Response
- Combined Voltage Feed-Forward and Average Current
Mode Control
• Overvoltage, Undervoltage and Overcurrent Protection
• Power-Good Output with internal blanking during VID and
mode changes
• User programmable Switching Frequency of 250kHz -
1MHz per phase
• Pb-Free Plus Anneal Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6217A
Ordering Information
PART NUMBER
ISL6217ACV
ISL6217ACV-T
ISL6217ACVZ
(Note 1)
ISL6217ACVZ-T
(Note 1)
ISL6217ACVZA
TEMP (°C)
-10 to 85
PACKAGE
38 Ld TSSOP
PKG.
DWG. #
M38.173
M38.173
M38.173
M38.173
M38.173
M38.173
Pinout
ISL6217A (38 LD TSSOP)
TOP VIEW
VDD 1
DACOUT 2
DSV 3
FSET 4
PWRCH 5
EN 6
DRSEN 7
DSEN# 8
VID0 9
VID1 10
VID2 11
VID3 12
VID4 13
VID5 14
PGOOD 15
EA+ 16
COMP 17
FB 18
SOFT 19
ISL6217A
TSSOP
38 VBAT
37 ISEN1
36 PHASE1
35 UG1
34 BOOT1
33 VSSP1
32 LG1
31 VDDP
30 LG2
29 VSSP2
28 BOOT2
27 UG2
26 PHASE2
25 ISEN2
24 VSEN
23 DRSV
22 STV
21 OCSET
20 VSS
38 Ld TSSOP Tape and Reel
-10 to 85
38 Ld TSSOP
(Pb-free)
38 Ld TSSOP Tape and Reel
(Pb-free)
-10 to 85
38 Ld TSSOP
(Pb-free)
ISL6217ACVZA-T 38 Ld TSSOP Tape and Reel
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2
FN9107.3
June 30, 2005
ISL6217A
Absolute Voltage Ratings
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . -0.3-+7V
Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V
Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35V
Phase1,2 and ISEN1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V
Boot1,2 with respect to Phase1,2 . . . . . . . . . . . . . . . . . . . . . . +6.5V
UGATE1,2 . . . . . . . . . . . . . . . (Phase1,2 - 0.3V) to (Boot1,2 + 0.3V)
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
TSSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . .
72°
Maximum Operating Junction Temperature.
. . . . . . . . . . . . . . 125°C
Maximum Storage Temperature Range
. . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s)
. . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 125°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air.
Electrical Specifications
PARAMETER
INPUT POWER SUPPLY
Operating Conditions: VDD = 5V, T
A
= -10°C to 85°C, Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
EN = 3.3V, DSEN# = 0, DRSEN = 0, PWRCH = 0
Input Supply Current, I(VDD)
EN = 0V
VDD Rising
VDD Falling
-
-
4.35
4.05
1.4
1
4.45
4.20
-
-
4.5
4.40
mA
µA
V
V
POR (Power-On Reset) Threshold
REFERENCE AND DAC
System Accuracy
Percent system deviation from programmed VID Codes @ 1.356
-0.8
-
0.7
-
-
-
-
-
1.708
0.70
0.8
0.3
-
-
-
%
V
V
V
V
DAC (VID0 - VID5) Input Low Voltage DAC Programming Input Low Threshold Voltage
DAC (VID0 - VID5) Input High
Voltage
Maximum Output Voltage
Minimum Output Voltage
CHANNEL GENERATOR
Frequency, FSW
Adjustment Range
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
ISEN
Full Scale Input Current
Overcurrent Threshold
Soft-Start Current
Droop Current
GATE DRIVER
UGATE Source Resistance
UGATE Source Current
500mA Source Current
VUGATE-PHASE = 2.5V
ROCSET = 124K
CL = 20pF
CL = 20pF
RFset = 243K, ±1%
Guaranteed by Design
DAC Programming Input High Threshold Voltage
225
0.25
250
-
275
1.0
kHz
MHz
-
-
-
100
18
4.0
-
-
-
dB
MHz
V/µs
-
-
-
27
32
64
31
28
-
-
-
30
µA
µA
µA
µA
-
-
1
2
1.5
-
Ω
A
3
FN9107.3
June 30, 2005
ISL6217A
Electrical Specifications
PARAMETER
UGATE Sink Resistance
UGATE Sink Current
LGATE Source Resistance
LGATE Source Current
LGATE Sink Resistance
LGATE Sink Current
BOOTSTRAP DIODE
Forward Voltage
POWER GOOD MONITOR
PGOOD Sense Current
PGOOD pull down MOSFET r
DS(ON)
(See Figure 10)
Undervoltage Threshold (Vsen/Vref)
Undervoltage Threshold (Vsen/Vref)
PGOOD Low Output Voltage
LOGIC THRESHOLD
EN, DSEN#, DRSEN Low
EN, DSEN#, DRSEN High
PROTECTION
Overvoltage Threshold (Vsen/Vref)
Delay Time
Delay Time from LGATE Falling to
UGATE Rising
Delay Time from UGATE Falling to
LGATE Rising
VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 2.5V,
LGATE = 2.5V
VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 2.5V,
LGATE = 2.5V
10
10
18
18
30
30
ns
ns
VSEN Rising
-
112.0
-
%
-
2
-
-
1
-
V
V
VSEN Rising
VSEN Falling
IPGOOD = 4mA
2.43
56
-
-
-
-
63
85.0
84.0
0.26
-
82
-
-
0.4
mA
Ω
%
%
V
VDDP = 5V, Forward Bias Current = 10mA
0.58
0.68
0.76
V
500mA Sink Current
VUGATE-PHASE = 2.5V
500mA Source Current
VLGATE = 2.5V
500mA Sink Current
VLGATE = 2.5V
Operating Conditions: VDD = 5V, T
A
= -10°C to 85°C, Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
-
-
-
-
-
-
TYP
1
2
1
2
0.5
4
MAX
1.5
-
1.5
-
0.8
-
UNITS
Ω
A
Ω
A
Ω
A
4
FN9107.3
June 30, 2005
ISL6217A
Functional Pin Description
VDD
- This pin is used to connect +5V to the IC to supply all
power necessary to operate the chip. The IC starts to
operate when the voltage on this pin exceeds the rising POR
threshold and shuts down when the voltage on this pin drops
below the falling POR threshold.
DACOUT
- This pin provides access to the output of the
Digital-to-Analog Converter.
DSV
- The voltage on this pin provides the set point for
output voltage during Deep Sleep Mode of operation.
FSET
- A resistor from this pin to ground programs the
switching frequency.
PWRCH
- This pin selects the number of power channels. A
HIGH logic level on this pin enables 2 channel operation,
and a LOW logic signal enables single channel operation.
EN -
This pin is connected to the system signal VR_ON and
provides the enable/disable function for the PWM controller.
DRSEN -
This pin connects to system logic “DPRSLPVR”
and enables Deeper Sleep mode of operation when a logic
HIGH is detected on this pin.
DSEN# -
This pin connects to system logic “STP_CPU#” and
enables Deep Sleep mode of operation. Deep Sleep is
enabled when a logic LOW signal is detected on this pin.
VID0, VID1, VID2, VID3, VID4, VID5 -
These pins are used
as inputs to the 6-bit Digital-to-Analog converter (DAC). VID0
is the least significant bit and VID5 is the most significant bit.
PGOOD -
This pin is used as an input and an output and is
tied to the Vccp and Vcc_mch PGOOD signals. During start-
up, this pin is recognized as an input and prevents further
slewing of the output voltage from the “Boot” level until
PGOOD from Vccp and Vcc_mch is enabled High. After
Start-up, this pin has an open drain output used to indicate
the status of the CORE output voltage. This pin is pulled low
when the system output is outside of the regulation limits.
PGOOD includes a timer for power-on delay.
EA+ -
This pin is connected to the non-inverting input of the
error amplifier and is used for setting the “Droop” voltage.
COMP -
This pin provides connection to the error amplifier
output.
FB -
This pin is connected to the inverting input of the error
amplifier.
SOFT
- This pin programs the slew rate of VID changes,
Deep Sleep and Deeper Sleep transitions and Soft-Start
after initializing. This pin is connected to ground via a
capacitor, and to EA+ through an external “Droop” resistor.
VBAT
- Voltage on this pin provides feed-forward battery
information which adjusts the oscillator ramp amplitude.
ISEN1, ISEN2
- These pins are used as current sense inputs
from the individual converter channel phase nodes.
PHASE1, PHASE2
- These pins are connected to the phase
nodes of channels 1 and 2, respectively.
UG1, UG2
- These pins are the gate-drive outputs to the
high side MOSFETs for channels 1 and 2, respectively.
BOOT1, BOOT2
- These pins are connected to the
bootstrap capacitors, for upper gate-drive, for channels 1
and 2, respectively.
VSSP1, VSSP2
- These pins are connected to the power
ground of channels 1 and 2, respectively.
LG1, LG2
- These pins are the gate-drive outputs to the low
side MOSFETs for channels 1 and 2, respectively.
VDDP
- This pin provides a low-esr bypass connection to the
internal gate drivers for the +5V source.
VSEN
- This pin is used for remote sensing of the
microprocessor CORE voltage.
DRSV
- The voltage on this pin provides the set point for
output voltage during Deeper Sleep Mode of operation.
OCSET
- A resistor from this pin to ground sets the
overcurrent protection threshold. The current from this pin
should be between 10µA and 25µA (70kΩ - 175kΩ
equivalent) pull-down resistance.
STV
- The voltage on this pin sets the initial Start-Up or
“Boot” voltage.
VSS
- This pin provides connection for signal ground.
5
FN9107.3
June 30, 2005
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