10M08DFV81C7G datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> Programmable logic devices> 10M08DFV81C7G

10M08DFV81C7G: DescriptionIC FPGA 56 I/O 81WLCSP; Categorysemiconductor Programmable logic devices; File Size577KB，69 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

Download Datasheet Parametric View All

10M08DFV81C7G Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	10M08DFV81C7G	-	-	View	Buy Now

10M08DFV81C7G Overview

IC FPGA 56 I/O 81WLCSP

10M08DFV81C7G Parametric

Parameter Name	Attribute value
Number of LABs/CLBs	500
Number of logic elements/units	8000
Total RAM bits	387072
Number of I/Os	56
Voltage - Power	1.15 V ~ 1.25 V
Installation type	surface mount
Operating temperature	0°C ~ 85°C（TJ）
Package/casing	81-UFBGA，WLCSP
Supplier device packaging	81-VBGA，WLCSP（4.5x4.4）

Preview

Download Datasheet

View All

Intel

MAX

10 Clocking and PLL

User Guide

Updated for Intel

Quartus

Prime Design Suite:

18.0

Send Feedback

UG-M10CLKPLL | 2018.06.15

Latest document on the web:

PDF

HTML

Contents

1. Intel

MAX

10 Clocking and PLL Overview................................................................... 4

1.1. Clock Networks Overview........................................................................................4

1.2. Internal Oscillator Overview.................................................................................... 4

1.3. PLLs Overview.......................................................................................................4

2. Intel MAX 10 Clocking and PLL Architecture and Features.............................................. 6

2.1. Clock Networks Architecture and Features................................................................6

2.1.1. Global Clock Networks................................................................................6

2.1.2. Clock Pins Introduction............................................................................... 6

2.1.3. Clock Resources........................................................................................ 7

2.1.4. Global Clock Network Sources..................................................................... 7

2.1.5. Global Clock Control Block.......................................................................... 9

2.1.6. Global Clock Network Power Down............................................................. 11

2.1.7. Clock Enable Signals................................................................................ 12

2.2. Internal Oscillator Architecture and Features........................................................... 13

2.3. PLLs Architecture and Features............................................................................. 13

2.3.1. PLL Architecture.......................................................................................13

2.3.2. PLL Features........................................................................................... 15

2.3.3. PLL Locations.......................................................................................... 15

2.3.4. Clock Pin to PLL Connections..................................................................... 17

2.3.5. PLL Counter to GCLK Connections.............................................................. 17

2.3.6. PLL Control Signals.................................................................................. 18

2.3.7. Clock Feedback Modes.............................................................................. 19

2.3.8. PLL External Clock Output......................................................................... 23

2.3.9. ADC Clock Input from PLL......................................................................... 24

2.3.10. Spread-Spectrum Clocking...................................................................... 24

2.3.11. PLL Programmable Parameters................................................................. 24

2.3.12. Clock Switchover....................................................................................27

2.3.13. PLL Cascading........................................................................................31

2.3.14. PLL Reconfiguration................................................................................ 32

3. Intel MAX 10 Clocking and PLL Design Considerations.................................................. 34

3.1. Clock Networks Design Considerations.................................................................... 34

3.1.1. Guideline: Clock Enable Signals................................................................. 34

3.1.2. Guideline: Connectivity Restrictions............................................................ 34

3.2. Internal Oscillator Design Considerations................................................................ 34

3.2.1. Guideline: Connectivity Restrictions............................................................ 34

3.3. PLLs Design Considerations................................................................................... 35

3.3.1. Guideline: PLL Control Signals................................................................... 35

3.3.2. Guideline: Connectivity Restrictions............................................................ 35

3.3.3. Guideline: Self-Reset................................................................................ 35

3.3.4. Guideline: Output Clocks...........................................................................36

3.3.5. Guideline: PLL Cascading.......................................................................... 36

3.3.6. Guideline: Clock Switchover...................................................................... 37

3.3.7. Guideline: .mif Streaming in PLL Reconfiguration..........................................38

3.3.8. Guideline: scandone Signal for PLL Reconfiguration...................................... 38

Intel

MAX

10 Clocking and PLL User Guide

Contents

4. Intel MAX 10 Clocking and PLL Implementation Guides................................................ 39

4.1. ALTCLKCTRL Intel FPGA IP Core............................................................................. 39

4.2. ALTPLL Intel FPGA IP Core.....................................................................................39

4.2.1. Expanding the PLL Lock Range...................................................................40

4.2.2. Programmable Bandwidth with Advanced Parameters....................................41

4.2.3. PLL Dynamic Reconfiguration Implementation.............................................. 42

4.2.4. Dynamic Phase Configuration Implementation............................................. 46

4.3. ALTPLL_RECONFIG Intel FPGA IP Core.................................................................... 49

4.3.1. Obtaining the Resource Utilization Report................................................... 49

4.4. Internal Oscillator Intel FPGA IP Core..................................................................... 50

5. ALTCLKCTRL Intel FPGA IP Core References................................................................ 51

5.1. ALTCLKCTRL IP Core Parameters............................................................................ 51

5.2. ALTCLKCTRL IP Core Ports and Signals....................................................................52

6. ALTPLL Intel FPGA IP Core References......................................................................... 53

6.1. ALTPLL IP Core Parameters....................................................................................53

6.1.1. Operation Modes Parameter Settings.......................................................... 53

6.1.2. PLL Control Signals Parameter Settings....................................................... 53

6.1.3. Programmable Bandwidth Parameter Settings.............................................. 54

6.1.4. Clock Switchover Parameter Settings.......................................................... 54

6.1.5. PLL Dynamic Reconfiguration Parameter Settings......................................... 55

6.1.6. Dynamic Phase Configuration Parameter Settings......................................... 55

6.1.7. Output Clocks Parameter Settings.............................................................. 56

6.2. ALTPLL IP Core Ports and Signals........................................................................... 57

7. ALTPLL_RECONFIG Intel FPGA IP Core References...................................................... 60

7.1. ALTPLL_RECONFIG IP Core Parameters................................................................... 60

7.2. ALTPLL_RECONFIG IP Core Ports and Signals........................................................... 61

7.3. ALTPLL_RECONFIG IP Core Counter Settings............................................................63

8. Internal Oscillator Intel FPGA IP Core References........................................................ 66

8.1. Internal Oscillator IP Core Parameters.................................................................... 66

8.2. Internal Oscillator IP Core Ports and Signals............................................................ 66

9. Intel MAX 10 Clocking and PLL User Guide Archives..................................................... 67

10. Document Revision History for the Intel MAX 10 Clocking and PLL User Guide........... 68

Intel

MAX

10 Clocking and PLL User Guide

Recommended Resources

Low-cost high-precision instrument amplification circuit diagram

Using op amp as power amplifier

High input resistance subtraction circuit

High power zero-crossing trigger timing power adjustment circuit

Human body infrared control switch circuit

Broadband Op Amp Circuit

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components