EEWORLDEEWORLDEEWORLD

Part Number

Search

SI2166-D60-GMR

Description
IC DEMODULATOR DVB 48QFN
Categorysemiconductor    Analog mixed-signal IC   
File Size41KB,2 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric Compare View All

SI2166-D60-GMR Online Shopping

Suppliers Part Number Price MOQ In stock  
SI2166-D60-GMR - - View Buy Now

SI2166-D60-GMR Overview

IC DEMODULATOR DVB 48QFN

SI2166-D60-GMR Parametric

Parameter NameAttribute value
typeDemodulator
applicationdigital video
Installation typesurface mount
Supplier device packaging48-QFN(7x7)
Si2166-D60
DVB-S/S2/S2X Digital TV Demodulator
Description
The Si2166D integrates digital demodulators for first and second
generation satellite DVB standards (DVB-S/S2 and S2X) in a
single advanced CMOS die. Leveraging Silicon Labs' proven
digital demodulation architecture, the Si2166D achieves excellent
satellite reception performance while significantly minimizing
front-end design complexity, cost, and power dissipation.
Connecting the Si2166D to a satellite silicon tuner results in a
high-performance and cost optimized TV or STB front-end
solution.
The satellite reception allows demodulating widespread DVB-S,
DIRECTV™ (DSS), DVB-S2, DIRECTV™ (AMC) legacy
standards, and new Part II of DVB-S2 (S2X) satellite broadcast
standard. A zero-IF interface (differential) allows for a seamless
connection to market proven satellite silicon tuners. Si2166D
embeds DiSEqC
TM
2.0 LNB interface for satellite dish control and
an equalizer to compensate for echoes in long cable feeds from
the antenna to the satellite tuner input.
The Si2166D offers an on-chip blind scan algorithm for DVB-S/S2/
S2X standards, as well as a blind lock function. The Si2166D
programmable transport stream output interface provides a flexible
range of output modes and is fully compatible with all MPEG
decoders or conditional access modules to support any customer
application.
Features
-
Pin-to-pin compatible with all Si216x/8x single demods family
-
API compatible with all single and dual demods families
-
DVB-S2 (ETSI EN 302 307-1 V1.4.1)
-
QPSK/8PSK demodulator
-
DVB-S2X (ETSI EN302 307-2 V1.1.1)
-
Support the normative broadcast services
-
QPSK/8PSK, 8/16/32APSKdemodulator
-
Roll-off factors from 0.05 to 0.35
-
VCM supported
-
ISSY and NPD supported
-
MIS supported
-
Output modes: TS, GPCS, and GSE-HEM supported
-
DVB-S and DSS supported
-
QPSK demodulator and enhanced FEC decoder
-
1 to 45 MSymbol/s for all satellite standards (<40 MSps in
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32APSK)
LDPC and BCH FEC decoding for DVB-S2/S2X standards
I
2
C serial bus interfaces (master and host)
Firmware control (embedded ROM/NVM)
Upgradeable with patch download via I
2
C or fast SPI
Flexible TS output interface (serial, parallel, and slave)
DiSEqC
TM
2.0 interface and Unicable
TM
support
Fast lock times
Low power consumption
Two power supplies: 1.2 and 3.3 V
7x7 mm, QFN-48 pin package, Pb-free/RoHS compliant
Full-NIM
iDTV (integrated Digital TV)
Digital satellite STB
PC-TV accessories
PVR, DVD, and Blue Ray disc recorders
Applications
DISEQC_OUT
DISEQC_IN
1.2, 3.3V
RESETB
DiSEqC
TM
2.0
QPSK/8PSK/xAPSK
S_ADC_IP
S_ADC_IN
S_ADC_QP
S_ADC_QN
MP_x
ADC (I)
ADC (Q)
FRONT
END
DSP &
SYNCHRO
CTRL
GPIO_0
GPIO
TS_ERR/
GPIO_1
INTERFACE
AGCs
LDPC
BCH
8
DVB-S/S2/S2X
FEC MODULE
Ext. Clk or Xtal
OSC
& PLL
CLK_IN_OUT
TUN_SDA
TUN_SCL
I
2
C
SWITCH
Si2166D
HOST_SDA
HOST_SCL
I
2
C
I/F
Digital Demodulator
Copyright © 2015 by Silicon Laboratories
HDTV MPEG S.o.C.
10.14.15
x(A)PSK
DEMOD
EQUAL-
IZER
MPEG TS
Satellite
ZIF Tuner
VITERBI
RS
TS_SYNC
TS_VAL
TS_CLK
TS_DATA

SI2166-D60-GMR Related Products

SI2166-D60-GMR SI2166-D60-GM
Description IC DEMODULATOR DVB 48QFN IC DEMODULATOR DVB 48QFN
Do you know the power supply solutions for tethered, aerial/underwater drones? Vicor engineers tell you!
Tethered, aerial/underwater drones These drones are powered and controlled from a ground power source via a tether. High-voltage tether transmission of 500V to 800V enables longer and thinner cables, ...
eric_wang Power technology
Implementing a 16-bit carry-lookahead adder using Verilog (Example)
module cla16 (a,b,s); //top module contains four 4-bit carry-lookahead adder submodules input [15:0] a, b; output [15:0] s; wire pp4,pp3,pp2,pp1; wire gg4,gg3,gg2,gg1; wire [14:0] Cp; wire [15:0] p,g;...
settleinsh FPGA/CPLD
What is the digital-to-analog conversion chip in DSP28335 used for?
It is DAC, usually using TLV5620 chip...
西里古1992 Microcontroller MCU
High-performance analog-to-digital converter AD6645 and its application
画中画广告开始Luxurious MCU development system 498 yuanFor stable video output:S3C2410 ARM9 development board 780 yuan DSP5402 learning development board II 200 yuanSummer discount: S3C44B0 development board...
fighting Analog electronics
Steps to register a company
Steps to register a company : 1. Choose the form of the company: For an ordinary limited liability company, the minimum registered capital is 30,000 yuan, and it requires 2 or more shareholders. From ...
fengzhang2002 Talking about work
Can anyone help me analyze this circuit?
It looks like a constant current source. Is there any expert who can analyze it?...
SXYDDD Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1190  799  1048  2326  457  24  17  22  47  10 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号