SN74LV20ANSRE4 datasheet, PDF - EEWORLD Datasheet

SN74LV20ANSRE4: DescriptionLogic Gates Dual 4-Input Positive-NAND Gate; Categorylogic logic; File Size458KB，15 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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Logic Gates Dual 4-Input Positive-NAND Gate

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	SOP, SOP14,.3
Contacts	14
Reach Compliance Code	unknow
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	10.2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	11.5 ns
propagation delay (tpd)	18.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5.3 mm

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