EEWORLDEEWORLDEEWORLD

Part Number

Search

ZGP323LAH4816G

Description
IC MCU 8BIT 16KB OTP 48SSOP
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size926KB,107 Pages
ManufacturerZilog, Inc.
Websitehttps://www.zilog.com/
Environmental Compliance
Download Datasheet Parametric View All

ZGP323LAH4816G Overview

IC MCU 8BIT 16KB OTP 48SSOP

ZGP323LAH4816G Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerZilog, Inc.
Parts packaging codeSSOP
package instructionSSOP, SSOP48,.4
Contacts48
Reach Compliance Codeunknown
Has ADCNO
Address bus width
bit size8
CPU seriesZ8
maximum clock frequency8 MHz
DAC channelNO
DMA channelNO
External data bus width
JESD-30 codeR-PDSO-G48
JESD-609 codee3
length15.875 mm
Humidity sensitivity level3
Number of I/O lines32
Number of terminals48
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
PWM channelNO
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP48,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Certification statusNot Qualified
RAM (bytes)237
rom(word)16384
ROM programmabilityOTPROM
Maximum seat height2.79 mm
speed8 MHz
Maximum slew rate10 mA
Maximum supply voltage3.6 V
Minimum supply voltage2 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width7.49 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
Z8 GP
TM
Microcontrollers
ZGP323H OTP MCU Family
Product Specification
PS023803-0305
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 •
www.ZiLOG.com
430 and PC serial port communication
How to connect MSP430F149 to PC via USB to serial port...
123xt Microcontroller MCU
FPGA DSP communication, using EMIF interface
Has anyone done FPGA-DSP communication? I use the EMIF interface. I use the internal fifo on the FPGA. How do I connect the fifo interface to the DSP pins? My current result is that the receiving is n...
wangyaoli FPGA/CPLD
Several classic FPGA verification books
SystemVerilog is a hardware description and verification language (HDVL). It is based on the IEEE1364-2001 Verilog hardware description language (HDL) and has been extended to include C language data ...
arui1999 Download Centre
One of the CPLD pins does not work
After the program is successfully burned, the trigger pin of the CPLD is always in a high-impedance state. The entire circuit is triggered as soon as it is powered on. I want to know whether it is a p...
xiaxuedehai FPGA/CPLD
Recommended: ARM/Linux/WinCE Lecture (Shanghai)
On July 21, it was held in the multifunctional conference room on the 6th floor of Building 1 of Shanghai University of Urban Management (50 meters straight after entering the door). Three topics: The...
chenye171 Linux and Android
Problems encountered when downloading DSP28335 with C2Prog
As the title says, please enlighten me :Cry:...
TLZme Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1595  2452  2640  1428  1204  33  50  54  29  25 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号