SN74LV10APW datasheet, PDF - EEWORLD Datasheet

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SN74LV10APW: DescriptionTriple 3-Input Positive-NAND Gate 14-TSSOP -40 to 85; Categorylogic logic; File Size856KB，14 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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SN74LV10APW Overview

Triple 3-Input Positive-NAND Gate 14-TSSOP -40 to 85

SN74LV10APW Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP14,.25
Contacts	14
Reach Compliance Code	compli
Factory Lead Time	1 week
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.012 A
Humidity sensitivity level	1
Number of functions	3
Number of entries	3
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Maximum supply current (ICC)	0.02 mA
Prop。Delay @ Nom-Su	13.5 ns
propagation delay (tpd)	20.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm

SN74LV10APW Related Products

	SN74LV10APW	SN74LV10AD	SN74LV10APWRG4	SN74LV10APWR	SN74LV10ANSR	SN74LV10ADRG4	SN74LV10ADR
Description	Triple 3-Input Positive-NAND Gate 14-TSSOP -40 to 85	Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 85	Triple 3-Input Positive-NAND Gate 14-TSSOP -40 to 85	Triple 3-Input Positive-NAND Gate 14-TSSOP -40 to 85	Triple 3-Input Positive-NAND Gate 14-SO -40 to 85	Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 85	Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 85
Brand Name	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Parts packaging code	TSSOP	SOIC	TSSOP	TSSOP	SOIC	SOIC	SOIC
package instruction	TSSOP, TSSOP14,.25	SOP, SOP14,.25	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25	SOP, SOP14,.3	SOP, SOP14,.25	SOP, SOP14,.25
Contacts	14	14	14	14	14	14	14
Reach Compliance Code	compli	compli	compli	compli	compli	compli	compli
Factory Lead Time	1 week	1 week	6 weeks	1 week	1 week	6 weeks	1 week
series	LV/LV-A/LVX/H	-	LV/LV-A/LVX/H	LV/LV-A/LVX/H	-	-	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14	-	R-PDSO-G14	R-PDSO-G14	-	-	R-PDSO-G14
JESD-609 code	e4	-	e4	e4	-	-	e4
length	5 mm	-	5 mm	5 mm	-	-	8.65 mm
Load capacitance (CL)	50 pF	-	50 pF	50 pF	-	-	50 pF
Logic integrated circuit type	NAND GATE	-	NAND GATE	NAND GATE	-	-	NAND GATE
MaximumI(ol)	0.012 A	-	0.012 A	0.012 A	-	-	0.012 A
Humidity sensitivity level	1	-	1	1	-	-	1
Number of functions	3	-	3	3	-	-	3
Number of entries	3	-	3	3	-	-	3
Number of terminals	14	-	14	14	-	-	14
Maximum operating temperature	85 °C	-	85 °C	85 °C	-	-	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-40 °C	-	-	-40 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY
encapsulated code	TSSOP	-	TSSOP	TSSOP	-	-	SOP
Encapsulate equivalent code	TSSOP14,.25	-	TSSOP14,.25	TSSOP14,.25	-	-	SOP14,.25
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	-	-	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	-	SMALL OUTLINE
method of packing	TUBE	-	TR	TR	-	-	TR
Peak Reflow Temperature (Celsius)	260	-	260	260	-	-	260
power supply	3.3 V	-	3.3 V	3.3 V	-	-	3.3 V
Maximum supply current (ICC)	0.02 mA	-	0.02 mA	0.02 mA	-	-	0.02 mA
Prop。Delay @ Nom-Su	13.5 ns	-	13.5 ns	13.5 ns	-	-	13.5 ns
propagation delay (tpd)	20.5 ns	-	20.5 ns	20.5 ns	-	-	20.5 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified	-	-	Not Qualified
Schmitt trigger	NO	-	NO	NO	-	-	NO
Maximum seat height	1.2 mm	-	1.2 mm	1.2 mm	-	-	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	-	5.5 V	5.5 V	-	-	5.5 V
Minimum supply voltage (Vsup)	2 V	-	2 V	2 V	-	-	2 V
Nominal supply voltage (Vsup)	2.5 V	-	2.5 V	2.5 V	-	-	2.5 V
surface mount	YES	-	YES	YES	-	-	YES
technology	CMOS	-	CMOS	CMOS	-	-	CMOS
Temperature level	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	-	-	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	-	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	-	-	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	-	GULL WING	GULL WING	-	-	GULL WING
Terminal pitch	0.65 mm	-	0.65 mm	0.65 mm	-	-	1.27 mm
Terminal location	DUAL	-	DUAL	DUAL	-	-	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	-	-	NOT SPECIFIED
width	4.4 mm	-	4.4 mm	4.4 mm	-	-	3.91 mm

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