a
FEATURES
12-Bit CMOS DAC with
On-Chip Voltage Reference
Output Amplifier
Three Selectable Output Ranges
–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
300 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Nonlinearity: 1/2 LSB T
MIN
to T
MAX
Low Power Dissipation: 100 mW Typical
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
REFOUT
LC MOS
12-Bit Serial DACPORT
AD7243
FUNCTIONAL BLOCK DIAGRAM
V
DD
2
2R
R
OFS
2R
V
OUT
12 - BIT DAC
REFIN
12
AGND
AD7243
DAC LATCH
12
DGND
INPUT SHIFT REGISTER
V
SS
SDIN CLR BIN/ SCLK SYNC LDAC DCEN SDO
COMP
GENERAL DESCRIPTION
The AD7243 is a complete 12-bit, voltage output, digital-to-
analog converter with output amplifier and Zener voltage refer-
ence on a monolithic CMOS chip. No external trims are
required to achieve full specified performance.
The output amplifier is capable of developing +10 V across a
2 kΩ load. The output voltage ranges with single supply opera-
tion are 0 V to +5 V or 0 V to +10 V, while an additional bipo-
lar
±
5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.
The data format is natural binary in both unipolar ranges, while
either offset binary or two’s complement format may be selected
in the bipolar range. A
CLR
function is provided which sets the
output to 0 V in both unipolar ranges and in the two’s comple-
ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the output to be set to a known voltage level.
The AD7243 features a fast versatile serial interface which
allows easy connection to both microcomputers and 16-bit digi-
tal signal processors with serial ports. The serial data may be
applied at rates up to 5 MHz allowing a DAC update rate of
300 kHz. A serial data output capability is also provided which
allows daisy chaining in multi-DAC systems. This feature allows
any number of DACs to be used in a system with a simple
4-wire interface. All DACs may be updated simultaneously
using
LDAC.
The AD7243 is fabricated on Linear Compatible CMOS
(LC
2
MOS), an advanced, mixed technology process. It is pack-
aged in 16-lead DIP and 16-lead SOIC packages.
PRODUCT HIGHLIGHTS
1. Complete 12-Bit DACPORT
®
The AD7243 is a complete, voltage output, 12-bit DAC on
a single chip. The single chip design is inherently more
reliable than multichip designs.
2. Single or Dual Supply Operation.
3. Minimum 3-wire interface to most DSP processors.
4. DAC Update Rate–300 kHz.
5. Serial Data Output allows easy daisy-chaining in multiple
DAC systems.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7243–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
3
Differential Nonlinearity
3
Unipolar Offset Error
3
Bipolar Zero Error
3
Full-Scale Error
3, 4
Full-Scale Temperature Coefficient
5
REFERENCE OUTPUT
Reference Output Range, REFOUT
Reference Temperature Coefficient
5
Reference Load Change
(∆REFOUT
VS
. I
L
)
REFERENCE INPUT
Reference Input Range, REFIN
Input Current
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance
5
DIGITAL OUTPUT
Serial Data Out (SDO)
Output Low Voltage, V
OL
Output High Voltage, V
OH
ANALOG OUTPUT
Output Range Resistor, R
OFS
Output Voltage Ranges
6
Output Voltage Ranges
6
DC Output Impedance
5
AC CHARACTERISTICS
5
Voltage Output Settling-Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
3
Digital Feedthrough
3
POWER REQUIREMENTS
V
DD
Range
V
SS
Range (Dual Supplies)
I
DD
I
SS
(Dual Supplies)
A
2
12
±
1
±
0.9
±
4
±
5
±
6
±
5
B
2
12
±
1/2
±
0.9
±
4
±
5
±
6
±
5
(V
DD
= +12 V to +15 V,
1
V
SS
= 0 V or –12 V to –15 V,
1
AGND = DGND = O V, REFIN = +5 V,
R
L
= 2 k , C
L
= 100 pF to AGND. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
S
2
12
±
1
±
0.9
±
5
±
6
±
7
±
5
Unit
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
ppm of FSR/
°C
typ
V min/V max
ppm/°C typ
mV max
V min/V max
µA
max
V min
V max
µA
max
pF max
Test Conditions/Comments
Guaranteed Monotonic
V
SS
= 0 V or –12 V to –15 V
1
; DAC Latch
Contents All 0s
V
SS
= –12 V to –15 V
1
; DAC Latch Contents All 0s
Guaranteed By Process
4.95/5.05
±
25
–1
4.95/5.05
5
2.4
0.8
±
1
8
4.95/5.05
±
25
–1
4.95/5.05
5
2.4
0.8
±
1
8
4.95/5.05
±
30
–1
4.95/5.05
5
2.4
0.8
±
1
8
Guaranteed By Process
Reference Load Current (I
L
) Change (0–100
µA)
5 V
±
1% for Specified Performance
V
IN
= 0 V to V
DD
0.4
4.0
15/30
+5, +10
+5, +10,
±5
0.5
0.4
4.0
15/30
+5, +10
+5, +10,
±
5
0.5
0.4
4.0
15/30
+5, +10
+5, +10,
±
5
0.5
V max
V min
kΩ min/max
V
V
Ω
typ
I
SINK
= 1.6 mA
I
SOURCE
= 400
µA
Typically 20 k . Guaranteed By Process
Single Supply; V
SS
= 0 V
Dual Supply; V
SS
= –12 V to –15 V
10
10
30
10
+10.8/+16.5
–10.8/–16.5
10
2
10
10
30
10
+10.8/+16.5
–10.8/–16.5
10
2
10
10
30
10
+11.4/+15.75
–11.4/–15.75
10
2
µs
max
µs
max
nV secs typ
nV secs typ
V min/V max
V min/V max
mA max
mA max
Settling Time to Within
±
1/2 LSB of Final Value
Typically 4
µs
Typically 5
µs
DAC Latch Contents Toggled Between All 0s
and All 1s
LDAC
= High
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; Typically 7 mA
Output Unloaded; Typically 1 mA
NOTES
1
Power Supply Tolerance A, B Versions:
±
10%; S Version:
±
5%.
2
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3
See terminology.
4
Measured with respect to REFIN and includes unipolar/bipolar offset error.
5
Guaranteed by design and characterization, not production tested.
6
0 V to +10 V output range is available only with V
DD
≥
+14.25 V.
Specifications subject to change without notice.
–2–
REV. A
AD7243
TIMING CHARACTERISTICS
Parameter
t
1 3
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
104, 5
t
114, 6
200
15
70
0
40
0
20
0
20
160
>t
5
1, 2
(V
DD
= +10.8 V to +16.5 V, V
SS
= 0 V or –10.8 V to –16.5 V, AGND = DGND = 0 V,
R
L
= 2 k , C
L
= 100 pF. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
Conditions/Comments
SCLK Cycle Time
SYNC
to SCLK Falling Edge Setup Time
SYNC
to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC
High to
LDAC
Low
LDAC
Pulsewidth
LDAC
High to
SYNC
Low
CLR
Pulsewidth
SCLK Falling Edge to SDO Valid
SCLK Falling Edge to SDO Invalid
Limit at +25 C, T
MIN
, T
MAX
(All Versions)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 7 & 8.
3
SCLK mark/space ratio range is 40/60 to 60/40.
4
SDO load capacitance is no greater than 50 pF.
5
At 25°C t
10
is 130 ns max.
6
Guaranteed by design.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND, DGND . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND, DGND . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT2
to AGND . . . . . . . . . . . . . . . . . . . –6 V to V
DD
+ 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
SDO to DGND . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2
The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.
ORDERING GUIDE
Model
AD7243AN
AD7243BN
AD7243AR
AD7243BR
AD7243AQ
AD7243BQ
AD7243SQ
2
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Relative Accuracy
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
Package Option
1
N-16
N-16
R-16
R-16
Q-16
Q-16
Q-16
NOTES
1
N = Plastic DIP; R = SOIC; Q = Cerdip.
2
Available to /883B processing only. Contact your local sales office for military data sheet.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7243 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD7243
TERMINOLOGY
Bipolar Zero Error
Relative Accuracy (Linearity)
Bipolar Zero Error is the voltage measured at V
OUT
when the
DAC is configured for bipolar output and loaded with all 0s
(Two’s Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale Error
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
The output amplifier on the AD7243 can have true negative off-
sets even when the part is operated from a single +15 V supply.
However, because the negative supply rail (V
SS
) is 0 V, the out-
put cannot actually go negative. Instead, when the output offset
voltage is negative, the output voltage sits at 0 V, resulting in the
transfer function shown in Figure 1.
This is the voltage spike that appears at V
OUT
when the digital
code in the DAC latch changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.
Digital Feedthrough
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
This is a measure of the voltage spike that appears on V
OUT
as a
result of feedthrough from the digital inputs on the AD7243. It
is measured with
LDAC
held high.
{
DAC CODE
Figure 1. Effect of Negative Offset (Single Supply)
AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)
Pin Mnemonic
1
2
3
4
REFIN
REFOUT
CLR
BIN/COMP
Description
Voltage Reference Input. It is internally buffered before being applied to the DAC. The nominal reference
voltage for specified operation of the AD7243 is 5 V.
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part -
using its internal reference, REFOUT should be connected to REFIN.
Clear, Logic Input. Taking this input low sets V
OUT
to 0 V in both unipolar ranges and the two’s complement
bipolar range and to –REFIN in the offset binary bipolar range.
Logic Input. This input selects the data format to be either binary or two’s complement. In both unipolar
ranges, natural binary format is selected by connecting this input to a Logic “0.” In the bipolar configuration,
offset binary format is selected with a Logic “0” while a Logic “1” selects two’s complement format.
Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a
new data word.
Digital Ground. Ground reference for all digital circuitry.
Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively if this line is permanently low, an automatic update mode is selected whereby the DAC
is updated on the 16th falling SCLK pulse.
Daisy-Chain Enable, Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise
this pin must be connected low.
Serial Data Out, Logic Output. With DCEN at Logic “1” this output is enabled, and the serial data in the
input shift register is clocked out on each falling SCLK edge.
Analog Ground. Ground reference for all analog circuitry.
Output Offset Resistor for the amplifier. It is connected to V
OUT
for the +5 V range, to AGND for the +10 V
range and to REFIN for the –5 V to +5 V range.
Analog Output Voltage. This is the buffer amplifier output voltage. Three different output voltage ranges can
be chosen: 0 V to +5 V, 0 to +10 V and –5 V to +5 V.
Negative Power Supply (used for the output amplifier only, may be connected to 0 V for single supply
operation or to –12 V to –15 V for dual supplies).
Positive Power Supply (+12 V to +15 V).
–4–
REV. A
5
6
7
8
9
SCLK
SDIN
SYNC
DGND
LDAC
10
11
12
13
14
15
16
DCEN
SDO
AGND
R
OFS
V
OUT
V
SS
V
DD
AD7243
TERMINOLOGY (Continued)
Internal Reference
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the out-
put voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7243 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
The AD7243 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V
±
50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter (by connecting the REFOUT pin to the REFIN pin.)
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500
µA
to an ex-
ternal load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference is re-
quired for external use with capacitive loads greater than 50 pF
then it should be decoupled to AGND with a 200
Ω
resistor in
series with a parallel combination of a 10
µF
tantalum capacitor
and a 0.1
µF
ceramic capacitor.
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±
1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
200
REFOUT
10 F
0.1 F
EXT
LOAD
Figure 3. Reference Decoupling Scheme
External Reference
Unipolar Offset Error is the measured output voltage from
V
OUT
with all zeros loaded into the DAC latch when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
PIN CONFIGURATION
DIP and SOIC
REFIN
REFOUT
1
2
16 V
DD
15 V
SS
In some applications, the user may require a system reference or
some other external reference to drive the AD7243. References
such as the AD586 provide an ideal external reference source
(see Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
degradation in linearity vs. REFIN.
1.0
V
DD
= +15V
V
SS
= –15V
T
A
= +25 C
CLR 3
BIN/COMP
4
AD7243
TOP VIEW
(Not to Scale)
14 V
OUT
13 R
OFS
12
11
10
9
AGND
0.9
0.8
SCLK 5
SDIN
SYNC
DGND
6
7
8
SDO
DCEN
LDAC
LINEARITY ERROR – LSBs
0.7
0.6
0.5
0.4
INL
0.3
0.2
DNL
0.1
0.0
2
3
4
5
6
REFIN – Volts
7
8
9
CIRCUIT INFORMATION
D/A Section
The AD7243 contains a 12-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The output voltage
from the converter has the same polarity as the reference volt-
age, REFIN, allowing single supply operation.
2R
R
OFS
R
R
2R
DB1
R
R
2R
DB9
R
2R
DB10
V
OUT
2R
DB11
2R
Figure 4. Typical Linearity vs. REFIN Voltage
Op Amp Section
2R
2R
DB0
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The R
OFS
input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
of developing +10 V across a 2 kΩ load to AGND.
The output amplifier can be operated from a single +12 V to
+15 V supply by tying V
SS
= 0 V.
The amplifier can also be operated from dual supplies to allow
an additional bipolar output range of –5 V to +5 V. Dual supplies are
necessary for the bipolar output range but can also be used for
the unipolar ranges to give faster settling time to voltages near
–5–
REFIN*
AGND
*BUFFERED REFIN VOLTAGE
SHOWN FOR ALL 1S
ON DAC
Figure 2. D/A Simplified Circuit Diagram
REV. A
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