SN74HCT00PWT datasheet, PDF - EEWORLD Datasheet

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SN74HCT00PWT: DescriptionLogic Gates Quadruple 2-Input Positive-NAND gates; Categorylogic logic; File Size390KB，12 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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SN74HCT00PWT Overview

Logic Gates Quadruple 2-Input Positive-NAND gates

SN74HCT00PWT Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP14,.25
Contacts	14
Reach Compliance Code	compli
Factory Lead Time	1 week
series	HCT
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.004 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TR
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Prop。Delay @ Nom-Su	25 ns
propagation delay (tpd)	25 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
Base Number Matches	1

SN74HCT00PWT Related Products

	SN74HCT00PWT	SN74HCT00PWTE4	SN74HCT00PWG4	SN74HCT00PWE4	SN74HCT00NSRE4	SN74HCT00DTE4
Description	Logic Gates Quadruple 2-Input Positive-NAND gates	Logic Gates Quadruple 2-Input Positive-NAND gates	Logic Gates Quadruple 2-Input Positive-NAND gates	Logic Gates Quadruple 2-Input Positive-NAND gates	Logic Gates Quadruple 2-Input Positive-NAND gates	Logic Gates Quadruple 2-Input Positive-NAND gates
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Parts packaging code	TSSOP	TSSOP	TSSOP	TSSOP	SOIC	SOIC
package instruction	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25	SOP, SOP14,.3	SOP, SOP14,.25
Contacts	14	14	14	14	14	14
Reach Compliance Code	compli	unknow	unknow	unknow	unknow	unknow
series	HCT	HCT	HCT	HCT	HCT	HCT
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4	e4	e4	e4
length	5 mm	5 mm	5 mm	5 mm	10.2 mm	8.65 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A
Humidity sensitivity level	1	1	1	1	1	1
Number of functions	4	4	4	4	4	4
Number of entries	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP	SOP	SOP
Encapsulate equivalent code	TSSOP14,.25	TSSOP14,.25	TSSOP14,.25	TSSOP14,.25	SOP14,.3	SOP14,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE
method of packing	TR	TR	TUBE	TUBE	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Su	25 ns	25 ns	25 ns	25 ns	25 ns	25 ns
propagation delay (tpd)	25 ns	25 ns	25 ns	25 ns	25 ns	25 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	2 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	4.4 mm	4.4 mm	4.4 mm	4.4 mm	5.3 mm	3.9 mm

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