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552AD000104DGR

Description
Oscillator, 10MHz Min, 945MHz Max, 156.25MHz Nom
CategoryPassive components   
File Size477KB,15 Pages
ManufacturerSilicon Laboratories Inc
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552AD000104DGR Overview

Oscillator, 10MHz Min, 945MHz Max, 156.25MHz Nom

552AD000104DGR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid113806295
Reach Compliance Codecompliant
Installation featuresSURFACE MOUNT
Number of terminals6
Maximum operating frequency945 MHz
Minimum operating frequency10 MHz
Nominal operating frequency156.25 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
Encapsulate equivalent codeDILCC6,.2
Certification statusNot Qualified
Maximum slew rate130 mA
Nominal supply voltage3.3 V
surface mountYES
Si 5 5 2
R
EVISION
D
D
U A L
F
REQUENCY
V
OLTAGE
- C
ON TROLLED
C
R Y S TA L
O
SCILLATOR
(VCXO) 10 MH
Z TO
1 . 4 G H
Z
Features
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Ordering Information:
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 10.
Description
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments typically found in communication
systems. The Si552 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Pin Assignments:
See page 9.
(Top View)
V
C
1
2
3
6
5
4
V
DD
FS
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK- CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
®
Clock Synthesis
ADC
V
C
FS
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si552
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