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LTC2264CUJ-14#TRPBF

Description
IC ADC 14BIT SER/PAR 40M 40-QFN
CategoryAnalog mixed-signal IC    converter   
File Size1MB,32 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Environmental Compliance
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LTC2264CUJ-14#TRPBF Overview

IC ADC 14BIT SER/PAR 40M 40-QFN

LTC2264CUJ-14#TRPBF Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?conform to
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN, LCC40,.24SQ,20
Contacts40
Manufacturer packaging codeUJ
Reach Compliance Codecompliant
ECCN code3A991.C.3
Maximum analog input voltage2 V
Minimum analog input voltage-2 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N40
JESD-609 codee3
length6 mm
Maximum linear error (EL)0.0183%
Humidity sensitivity level1
Number of analog input channels2
Number of digits14
Number of functions1
Number of terminals40
Maximum operating temperature70 °C
Minimum operating temperature
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatSERIAL
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC40,.24SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8 V
Certification statusNot Qualified
Sampling rate40 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width6 mm
LTC2265-14/
LTC2264-14/LTC2263-14
14-Bit, 65Msps/40Msps/
25Msps Low Power Dual ADCs
FEATURES
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DESCRIPTION
The LTC
®
2265-14/LTC2264-14/LTC2263-14 are 2-channel,
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.7dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 1.2LSB
RMS
.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
2-Channel Simultaneous Sampling ADC
73.7dB SNR
90dB SFDR
Low Power: 171mW/113mW/94mW Total
85mW/56mW/47mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm
×
6mm) QFN Package
APPLICATIONS
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Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V
DD
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
1.8V
OV
DD
OUT1A
OUT1B
AMPLITUDE (dBFS)
DATA
SERIALIZER
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
GND
OGND
226514 TA01
LTC2265-14, 65Msps,
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
–30
SERIALIZED
LVDS
OUTPUTS
–40
–50
–60
–70
–80
+
S/H
+
S/H
14-BIT
ADC CORE
14-BIT
ADC CORE
PLL
–90
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
226514
TA02
22654314fb
1

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