DF6F6.8MCTC
ESD Protection Diodes
Silicon Epitaxial Planar
DF6F6.8MCTC
1. Applications
•
ESD Protection
This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other
purpose, including, but not limited to, voltage regulation.
Note:
2. Features
(1)
(2)
(3)
ESD protection for up to 4 high-speed data lines and 1 V
BUS
line.
Ultra compact packaging for easy configuration in any ESD protection circuits.
Low Input/output-to-ground capacitance: C
t(1)
= 0.6 pF (typ.).
3. Packaging and Internal Circuit
1: I/O 1
2: GND
3: I/O 2
4: I/O 3
5: V
BUS
6: I/O 4
CST6C
4. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Electrostatic discharge voltage (IEC61000-4-2)(Contact)
Junction temperature
Storage temperature
Symbol
V
ESD
T
j
T
stg
Rating
±8
150
-55 to 150
Unit
kV
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
1
2013-10-30
Rev.3.0
DF6F6.8MCTC
5. Electrical Characteristics (Unless otherwise specified, T
a
= 25
)
V
RWM
: Working peak reverse
voltage
V
BR
: Reverse breakdown voltage
I
BR
: Reverse breakdown current
I
R
: Reverse current
V
C
: Clamp voltage
I
PP
: Peak pulse current
R
DYN
: Dynamic resistance
I
F
: Forward current
V
F
: Forward voltage
Fig. 5.1 Definitions of Electrical Characteristics
Characteristics
Working peak reverse voltage
Reverse breakdown voltage
Symbol
V
RWM
V
BR(1)
V
BR(2)
Reverse current
I
R(1)
I
R(2)
Clamp voltage
V
C(1)
V
C(2)
V
C(3)
V
C(4)
Dynamic resistance
Total capacitance
Note
I
BR
= 5 mA
(between I/O and GND)
I
BR
= 5 mA
(between V
BUS
and GND)
V
RWM
= 5 V
(between I/O and GND)
V
RWM
= 5 V
(between V
BUS
and GND)
(Note 1) I
PP
= 1 A
(between I/O and GND)
(Note 1) I
PP
= 2.5 A
(between I/O and GND)
(Note 1) I
PP
= 1 A
(between V
BUS
and GND)
(Note 1) I
PP
= 9 A
(between V
BUS
and GND)
Test Condition
Min
6.0
6.8
Typ.
15
18
14
25
0.9
0.6
0.6
67
0.3
0.01
Max
5.0
0.5
0.5
20
24
19
30
1.0
Unit
V
V
V
µA
µA
V
V
V
V
Ω
Ω
pF
pF
pF
pF
R
DYN(1)
(Note 2) (between I/O and GND)
R
DYN(2)
(Note 2) (between V
BUS
and GND)
C
t(1)
C
t(2)
C
t(3)
(Note 3) V
R
= 0 V, f = 1 MHz
(between I/O and GND)
V
R
= 0 V, f = 1 MHz
(between V
BUS
and GND)
V
R
= 0 V, f = 1 MHz
(between I/O and I/O)
V
R
= 0 V, f = 1 MHz
(between I/O and GND)
Input/output-to-ground capacitance
∆C
t-GND
difference
Note 1: Based on IEC61000-4-5 8/20
µs
pulse.
Note 2: TLP parameter: Z0 = 50
Ω,
tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using a least-squares fit of TLP characteristics at I
PP
between 3 A to 8 A.
Note 3: Guaranteed by design.
2
2013-10-30
Rev.3.0
Analog electronics
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