AT97SC3205T
Trusted Platform Module
I
2
C Interface
SUMMARY DATASHEET
Features
Compliant to the Trusted Computing Group (TCG) Trusted Platform Module
(TPM) Version 1.2 Specification
Single-chip Turnkey Solution
Hardware Asymmetric Crypto Engine
Atmel AVR
®
RISC Microprocessor
Internal EEPROM Storage for RSA Keys
400kHz Fast Mode/100kHz Standard Mode I
2
C Operation
Secure Hardware and Firmware Design and Device Layout
FIPS-140-2 Module Certified Including the High-quality Random Number
Generator (RNG), HMAC, AES, SHA, and RSA Engines
NV Storage Space for 2066 bytes of User Defined Data
3.3V Supply Voltage
28-lead Thin TSSOP or 32-pad QFN Packages
Offered in Commercial (0C to 70C) and Industrial (-40 to +85C)
Temperature Range
Description
Atmel AT97SC3205T is a fully integrated security module designed to be
integrated into embedded systems. It implements version 1.2 of the Trusted
Computing Group (TCG) specification for Trusted Platform Modules (TPM).
This is a summary document.
The complete document is
available under NDA. For more
information, please contact
your local Atmel sales office.
Atmel-8883AS-TPM-AT97SC3205T-Datasheet-Summary_022014
1.
Pin Configuration and Pinouts
Table 1-1.
Pin Name
V
CC
GND
LRESET#
SM_DAT
SM_CLK
GPIO
GPIO-Express-00
PP/GPIO
TestI
TestBI/GPIO/XTAMPER
TWI_Wakeup#
PIRQ#
ATest
NC
Pin Configurations
Description
3.3V Supply Voltage
Ground
Reset Input Active Low
Serial Data Input/Output
Serial Clock Input
General Purpose Input/Output
GPIO Assigned to TPM_NV_INDEX_GPIO_00
Hardware Physical Presence or GPIO Pin
Test Input (Disabled)
Test Input (Disabled) / XTAMPER / GPIO Pin
Low-Power Sleep Recovery (Active Low)
SPI Interrupt Requests
Atmel Test Pin
No Connect
Figure 1-1.
Pinout Diagrams
28-pin TSSOP
4.40mm x 9.70mm Body
0.65mm Pitch
32-pin QFN
4.00mm x 4.00mm Body
0.40mm Pitch
31 NC
28 NC
27 NC
26 NC
NC 15
SM_CLK
V
CC
GND
NC
GPIO-Express-00
PP/GPIO/TWI_Wakeup#
TestI*
TestBI/GPIO/XTAMPER
V
CC
2
3
4
5
6
7
8
9
10
27 NC
26 ATest*
25 GND
24 V
CC
23 ATest*
22 TWI_Wakeup#
21 ATest*
20 PIRQ#
19 V
CC
18 GND
17 GPIO
16 LRESET#
15 NC
V
CC
GND
GPIO-Express-00
PP/GPIO/TWI_Wakeup#
TestI*
TestBI/GPIO/XTAMPER
NC
V
CC
1
2
3
4
5
6
7
8
NC 10
GPIO 12
NC 13
NC 14
NC 13
NC 14
Note:
* Used for Atmel internal testing only. Tie to V
CC
or GND directly or through a 4.7K resistor.
2
AT97SC3205T [SUMMARY DATASHEET]
Atmel-8883AS-TPM-AT97SC3205T-Datasheet-Summary_022014
GND
GND 11
NC 12
NC 16
NC 11
9
25 NC
SM_DAT
1
28 NC
29 SM_CLK
30 SM_DAT
32 GND
24 ATest*
23 GND
22 V
CC
21 ATest*
20 TWI_Wakeup#
19 ATest*
18 PIRQ#
17 LRESET#
Table 1-2.
Pin
Pin Descriptions
Description
Power Supply, 3.3V.
Care should be taken to prevent excessive noise. Effective decoupling of the V
CC
inputs to the Atmel TPM is critical to assure consistently reliable operation over the lifetime of the
system. The Atmel recommendation is for a decoupling bypass capacitor within the range of 2200pF to
4700pF to be placed as close as possible <5mm to each of the V
CC
pins; located between each V
CC
pin
and the immediately adjacent GND pin. A 0.1μF decoupling bypass capacitor should be placed at the
node in which these V
CC
traces join as close as possible; <10mm to the TPM. In all cases, this bypass
capacitor should be closer than the next closest component. All capacitors should be of high quality with
dielectric ratings of X5R or X7R. A low-power state is automatically entered when the device is idle. No
further action is required by the system to enter low-power mode.
System Ground.
Reset Active-Low.
Pulsing this signal low resets the internal state of the TPM and is equivalent to
removal/restoration of power to the device. The required minimum reset pulse width is 2μs. On power-
up, it is critical that Reset be kept active low until V
CC
stabilizes.
I
2
C Data Input/Output.
This pin serves as the Data Input/Output for the TPM. If one attempts to
communicate over the interface at close to the rated speed of 400kHz, the size of the pull-ups on
SM_DAT can be critical. A known value that functions properly at 400kHz is 800 on the SM_DAT line.
One may experiment with different pull-up values and/or reduce the clock rate if desired.
I
2
C Clock Input.
This pin serves as the Serial Clock Input to the TPM. If one attempts to communicate
over the interface at close to the rated speed of 400kHz, the size of the pull-ups on SM_CLK can be
critical. A known value that functions properly at 400kHz is 1.5K on the SM_CLK line. One may
experiment with different pull-up values and/or reduce the clock rate if desired.
The TPM communication stability is increased the closer to a 50% duty cycle on the SM_CLK signal
that can be provided. Although this becomes more critical at the rated speed of 400kHz, improvements
from a 50% duty cycle can result at lower speeds as well.
V
CC
GND
LRESET#
SM_DAT
SM_CLK
GPIO
General Purpose Input/Output.
If not used, tie high or low.
General Purpose Input/Output.
Internal pull-up resistor. This pin is mapped to NV Index
TPM_NV_INDEX_GPIO_00 and serves as the GPIO-Express-00. Default TPM configuration: GPIO
Input. GPIO-Express-00 also serves as the XOR chain Output during I/O test mode. Since
GPIO-Express-00 has an internal pull-up it should be left floating if unused.
General Purpose Input/Output.
Internal pull-down resistor. This pin is an indicator for hardware
physical presence; active high. Default TPM configuration: GPIO input. Since PP/GPIO has an internal
pull-down, it should be left floating if unused.
Test Input.
TestI manufacturing test input disabled after manufacturing. Tie TestI to ground directly or
through a 4.7K resistor.
Test Input.
The Atmel TPM does not support legacy addressing via the optional BADD implementation
of this pin.The TestBI pin serves as the XTAMPER pin or an additional GPIO pin, active high. (See the
application note, “Atmel Specific TPM Commands Reference Guide,” for details on XTAMPER
implementation). If unused, this pin should be tied to ground directly or through a 4.7K resistor.
Low-Power Sleep Recovery.
These two pins serve as the mechanism to allow the TPM to recover
from its low-power sleep state after receiving the Atmel Specific command TPM_DeepSleep (See Atmel
TPM Specific Commands document for further details). These pins must both be pulsed active low in
order to recover from the low-power sleep state. If unused, pin 7 can be left floating or tied to GND
either directly or through a 4.7K resistor. Pin 22 should be tied to GND or V
CC
either directly or through
a 4.7K resistor.
GPIO-Express-00
PP/GPIO
TestI
TestBI/GPIO/
XTAMPER
TWI_Wakeup#
AT97SC3205T [SUMMARY DATASHEET]
Atmel-8883AS-TPM-AT97SC3205T-Datasheet-Summary_022014
3
Table 1-2.
Pin
PIRQ#
Pin Descriptions (Continued)
Description
SPI Interrupt Requests.
If unused, this pin should be tied to ground directly or through a 4.7K
resistor.
Atmel Test Pins.
Only utilized during manufacturing test.
To optimize power savings and improve noise immunity, these ATest pins should be biased to V
CC
or
GND as follows:
TSSOP Pin 21 / QFN Pin 19
TSSOP Pin 23 / QFN Pin 21
TSSOP Pin 26 / QFN Pin 24
No Connect Pins.
The AT97SC3205T TSSOP package has additional pins which are no connects and can be tied to
GND, V
CC
, or left floating at the customers discretion:
NC – TSSOP Pin 5
NC – TSSOP Pin 12
NC – TSSOP Pin 13
NC – TSSOP Pin 14
NC – TSSOP Pin 15
NC – TSSOP Pin 27
NC – TSSOP Pin 28
The AT97SC3205T QFN package has additional pins which are no connects and can be tied to GND,
V
CC
, or left floating at the customers discretion:
NC – QFN Pin 7
NC – QFN Pin 10
NC – QFN Pin 11
NC – QFN Pin 13
NC – QFN Pin 14
NC – QFN Pin 15
NC – QFN Pin 16
NC – QFN Pin 25
NC – QFN Pin 26
NC – QFN Pin 27
NC – QFN Pin 28
NC – QFN Pin 31
ATest
NC
Note:
1.
The substrate center pad for the 32-pin QFN is directly tied to GND internally; therefore, this pad can either be left
floating or tied to GND.
4
AT97SC3205T [SUMMARY DATASHEET]
Atmel-8883AS-TPM-AT97SC3205T-Datasheet-Summary_022014
2.
Block Diagram
ROM
Program
EEPROM
Program
AVR
8-bit RISC
CPU
PP/GPIO
GPIO Express-00
SRAM
GPIO
EEPROM
Data
SM_DAT
SM_CLK
I
2
C
RNG
CRYPTO
Engine
Timer
Physical
Security
Circuitry
Communication to and from the TPM occurs through a 400kHz Fast mode/100kHz Standard mode. The TPM
includes a hardware random number generator, including a FIPS certified Pseudo Random Number Generator
which is used for key generation and TCG protocol functions. The RNG is also available to the system to generate
random numbers which may be needed during normal operation.
The device uses a dynamic internal memory management scheme to store multiple RSA keys. Other than the
standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2), no system intervention is required to manage
this internal key cache.
Full documentation for TCG primitives can be found in the TCG TPM Main Specification, Parts 1 – 3, on the TCG
Web site located at
www.trustedcomputinggroup.org.
This specification includes only mechanical, electrical and
I
2
C protocol information.
AT97SC3205T [SUMMARY DATASHEET]
Atmel-8883AS-TPM-AT97SC3205T-Datasheet-Summary_022014
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
