FemtoClock
®
Crystal/LVCMOS-to-
LVDS/LVCMOS Frequency Synthesizer
ICS8440258I-45
DATA SHEET
General Description
The ICS8440258I-45 is a eight output synthesizer optimized to
generate Gigabit and 10 Gigabit Ethernet clocks. Using a 25MHz,
18pF parallel resonant crystal, the device will generate both
156.25MHz and 125MHz clocks with mixed LVDS and LVCMOS/
LVTTL output levels. The ICS8440258I-45 uses IDT’s 3
RD
generation low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Ethernet jitter requirements.
The ICS8440258I-45 is packaged in a small, 5mm x 5mm VFQFN
package that is optimum for applications with space limitations.
Features
•
•
•
•
•
•
•
•
One differential LVDS output at 156.25MHz or 125MHz
Four differential LVDS outputs at 125MHz
Three LVCMOS/LVTTL single-ended outputs at 125MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input and PLL bypass from a single select pin
VCO range: 490MHz - 680MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical), LVDS outputs
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.43ps (typical), Q0, nQ0 output
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nPLL_BYPASS
Pullup
F_SEL
Pulldown
REF_CLK
Pulldown
25MHz
0
0
Q0
nQ0
XTAL_IN
Phase
Detector
1
VCO
490-680MHz
÷5
÷4
1
OSC
XTAL_OUT
0
Q1
nQ1
Q2
nQ2
Pin Assignment
nPLL_BYPASS
÷5
÷25
1
XTAL_OUT
REF_CLK
XTAL_IN
F_SEL
GND
V
DDA
V
DD
Q3
nQ3
32 31 30 29 28 27 26 25
Q0
nQ0
GND
Q1
nQ1
V
DDO_LVDS
Q2
nQ2
1
2
3
4
5
6
7
8
9
GND
24
23
nc
V
DDO_LVCMOS
Q7
GND
Q6
V
DDO_LVCMOS
Q5
GND
Q4
nQ4
Q5
ICS8440258I-45
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
10 11 12 13 14 15 16
nQ4
GND
V
DDO_LVDS
nQ3
V
DD
Q3
Q4
22
21
20
19
18
17
Q6
Q7
ICS8440258AKI-45 REVISION A APRIL 28, 2011
1
©2011 Integrated Device Technology, Inc.
ICS8440258I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2
3, 9, 15,
17, 21, 32
4, 5
6, 12
7, 8
10, 11
13, 14
16, 27
18, 20, 22
19, 23
24
25
26
28
29
30,
31
Name
Q0, nQ0
GND
Q1, nQ1
V
DDO_LVDS
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
DD
Q5, Q6, Q7
V
DDO_LVCMOS
nc
V
DDA
nPLL_BYPASS
F_SEL
REF_CLK
XTAL_IN,
XTAL_OUT
Output
Power
Output
Power
Output
Output
Output
Power
Output
Power
Unused
Power
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Type
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Output supply pins for Q[0:4], nQ[0:4] LVDS outputs.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pins.
Single-ended clock outputs.LVCMOS/LVTTL interface levels.
Output supply pins for Q[5:7] LVCMOS outputs.
No connect.
Analog supply pin.
Input select and PLL bypass control pin. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Q[5:7]
V
DDO_LVCMOS
= 2.625V
Q[5:7]
V
DDO_LVCMOS
= 2.625V
Test Conditions
Minimum
Typical
4
15
51
51
25
Maximum
Units
pF
pF
k
Ω
k
Ω
Ω
ICS8440258AKI-45 REVISION A APRIL 28, 2011
2
©2011 Integrated Device Technology, Inc.
ICS8440258I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Function Tables
Table 3A. F_SEL Frequency Select Function Table
Input
F_SEL
0
1
Output Divider Value
÷5
÷4
Output Frequency
Q0, nQ0 (MHz)
125 (default)
156.25
Table 3B. PLL Bypass and Input Select Function Table
Inputs
nPLL_BYPASS
0
1
PLL BYPASS
PLL Bypassed
PLL Enabled
Input Selected
REF_CLK
XTAL_IN, XTAL_OUT (default)
ICS8440258AKI-45 REVISION A APRIL 28, 2011
3
©2011 Integrated Device Technology, Inc.
ICS8440258I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_LVCMOS
+ 0.5V
10mA
15mA
-40°C to +85°C
33.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_LVCMOS,
V
DDO_LVDS
I
DD
I
DDA
I
DDO_LVCMOS
I
DDO_LVDS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
LVCMOS Output Supply Current
LVDS Output Supply Current
Test Conditions
Minimum
2.375
V
DD
–0.32
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
125
32
5
150
Units
V
V
V
mA
mA
mA
mA
ICS8440258AKI-45 REVISION A APRIL 28, 2011
4
©2011 Integrated Device Technology, Inc.
ICS8440258I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO_LVCMOS
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
Output
High Voltage
Output
Low Voltage
REF_CLK, F_SEL
nPLL_BYPASS
REF_CLK, F_SEL
nPLL_BYPASS
Q[5:7]
Q[5:7]
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
-5
-150
2.6
0.5
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
5
Units
V
V
µA
µA
µA
µA
V
V
I
IL
V
OH
V
OL
I
OH
= -12mA
I
OL
= 12mA
Table 4C. LVDS DC Characteristics,
V
DD
= V
DDO_LVDS
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.25
1.35
Test Conditions
Minimum
300
Typical
400
Maximum
545
50
1.5
50
Units
mV
mV
V
mV
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
Shunt Capacitance
Drive Level
Test Conditions
Minimum
Typical
Fundamental
25
50
7
1
MHz
Maximum
Units
Ω
pF
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
ICS8440258AKI-45 REVISION A APRIL 28, 2011
5
©2011 Integrated Device Technology, Inc.
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