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2
FPGA-DS-02012-1.9
ECP5™ and ECP5-5G™ Family
Data Sheet
Contents
Acronyms in This Document ................................................................................................................................................. 9
General Description .................................................................................................................................................... 10
Features ............................................................................................................................................................ 10
Modes of Operation...................................................................................................................................... 17
Clock Distribution Network ............................................................................................................................... 19
Bus Size Matching ......................................................................................................................................... 25
RAM Initialization and ROM Operation ........................................................................................................ 25
PIO ..................................................................................................................................................................... 32
DDR Memory Support ....................................................................................................................................... 35
DQS Grouping for DDR Memory ............................................................................................................... 35
DLL Calibrated DQS Delay and Control Block (DQSBUF)........................................................................... 36
Hot Socketing ........................................................................................................................................... 40
SERDES and Physical Coding Sublayer ............................................................................................................... 41
Density Shifting ................................................................................................................................................. 46
DC and Switching Characteristics ............................................................................................................................... 47
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02012-1.9
3
ECP5™ and ECP5-5G™ Family
Data Sheet
Absolute Maximum Ratings ..............................................................................................................................47
Power Supply Ramp Rates.................................................................................................................................48
Power-On-Reset Voltage Levels ........................................................................................................................48
Power up Sequence ...........................................................................................................................................48
Hot Socketing Specifications .............................................................................................................................48
Hot Socketing Requirements .............................................................................................................................49
DC Electrical Characteristics ..............................................................................................................................49
Supply Current (Standby) ..................................................................................................................................50
Maximum I/O Buffer Speed ..............................................................................................................................63
SERDES High-Speed Data Receiver ....................................................................................................................74
Input Data Jitter Tolerance ................................................................................................................................74
PCI Express Electrical and Timing Characteristics..............................................................................................76
PCIe (2.5 Gb/s) AC and DC Characteristics ................................................................................................76
PCIe (5 Gb/s) – Preliminary AC and DC Characteristics ............................................................................77
CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary....................................................................79
XAUI/CPRI LV E.30 Electrical and Timing Characteristics ..................................................................................80
AC and DC Characteristics ........................................................................................................................80
CPRI LV E.24/SGMII(2.5Gbps) Electrical and Timing Characteristics .................................................................80
AC and DC Characteristics ........................................................................................................................80
Gigabit Ethernet/SGMII(1.25Gbps)/CPRI LV E.12 Electrical and Timing Characteristics ...................................81
AC and DC Characteristics ........................................................................................................................81
SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics ...............................82
AC and DC Characteristics ........................................................................................................................82
sysCONFIG Port Timing Specifications ..............................................................................................................83
JTAG Port Timing Specifications ........................................................................................................................88
Switching Test Conditions .................................................................................................................................89
Pinout Information .....................................................................................................................................................91
Signal Descriptions ............................................................................................................................................91
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ........................................................94
Pin Information Summary .................................................................................................................................94
Ordering Information ..................................................................................................................................................97
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
FPGA-DS-02012-1.9
ECP5™ and ECP5-5G™ Family
Data Sheet
ECP5/ECP5-5G Part Number Description .......................................................................................................... 97
Ordering Part Numbers ..................................................................................................................................... 98
Supplemental Information ............................................................................................................................................... 102
For Further Information................................................................................................................................................ 102
Revision History ................................................................................................................................................................ 103
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Analogue and Mixed Signal
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