UVEPROM
Austin Semiconductor, Inc.
512K UVEPROM
UV Erasable Programmable
Read-Only Memory
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-87648
• MIL-STD-883
SMJ27C512
PIN ASSIGNMENT
(Top View)
28-Pin DIP (J) 600-Mils
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A14
A13
A8
A9
A11
G\/V
PP
A10
E\
DQ7
DQ6
DQ5
DQ4
DQ3
FEATURES
• Organized 65,536 x 8
• High-reliability MIL-PRF-38535 processing
• Single +5V ±10% power supply
• Pin-compatible with existing 512K read-only memories (ROMs)
and electrically programmable ROMs (EPROMs)
• All inputs/outputs fully TTL compatible
• Power-saving CMOS technology
• Very high-speed SNAP! Pulse Programming
• 3-state output buffers
• 400mV minimum DC noise immunity with standard TTL loads
• Latchup immunity of 250mA on all input and output lines
• Low power dissipation (CMOS input levels)
PActive
- 193mW (MAX)
PStandby
- 1.7mW (MAX)
Pin Name
A0 - A15
DA0-DQ7
E\
GND
G\ /V
PP
V
CC
Function
Address Inputs
Inputs (programming)/Outputs
Chip Enable/Power Down
Ground
Output Enable/13V Programming
5V Power Supply
OPTIONS
•
Timing
150ns access
200ns access
250ns access
• Package(s)
Ceramic DIP (600mils)
MARKING
-15
-20
-25
GENERAL DESCRIPTION
The SMJ27C512 is a set of 65536 by 8-bit (524,288-bit),
ultraviolet (UV) light erasable, electrically programmable
read-only memories. These devices are fabricated using
power-saving CMOS technology for high speed and simple
interface with MOS and bipolar circuits. All inputs
(including program data inputs can be driven by Series 54 TTL
circuits without the use of external pullup resistors. Each
output can drive one Series 54 TTL circuit without external
resistors. The data outputs are 3-state for connecting
multiple devices to a common bus. The SMJ27C512 is
pin-compatible with existing 28-pin 512K ROMs and
EPROMs.
Because this EPROM operates from a single 5V supply (in
the read mode), it is ideal for use in microprocessor-based
systems. One other supply (13V) is needed for programming.
All programming signals are TTL level. This device is
programmable by the SNAP! Pulse programming algorithm.
The SNAP! Pulse programming algorithm uses a V
PP
of 13V
and a V
CC
of 6.5V for a nominal programming time of seven
seconds. For programming outside the system, existing
EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
J
No. 110
• Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
M
For more products and information
please visit our web site at
www.austinsemiconductor.com
SMJ27512
Rev. 1.0 9/01
1
UVEPROM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM*
EPROM 65,536 x 8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
E\
G\ /V
PP
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
20
22
0
SMJ27C512
A
0
65,535
A
A
A
A
A
A
A
A
11
12
13
15
16
17
18
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
15
[PWR DWN]
&
EN
* This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
OPERATION
The seven modes of operation for the SMJ27C512 are listed in Table 1. The read mode requires a single 5V supply. All
inputs are TTL level except for V
PP
during programming (13V for SNAP! Pulse), and 12V on A9 for signature mode.
TABLE 1. OPERATION MODES
FUNCTION
(PINS)
E\ (20)
G\ /V
PP
(22)
V
CC
(28)
A9 (24)
A0 (10)
MODE*
READ
V
IL
V
IL
V
CC
X
X
OUTPUT
PROGRAM
SIGNATURE MODE
STANDBY PROGRAMMING VERIFY
DISABLE
INHIBIT
V
IL
V
IL
V
IH
V
IL
V
IL
V
IH
V
IH
V
CC
X
X
High-Z
X
V
CC
X
X
High-Z
V
PP
V
CC
X
X
Data In
V
IL
V
CC
X
X
Data Out
V
PP
V
CC
X
X
High-Z
V
ID
V
IL
V
IL
V
CC
V
ID
V
IH
DQ0-DQ7
Data Out
(11-13, 15-19)
* X can be V
IL
or V
IH
SMJ27512
Rev. 1.0 9/01
CODE
MFG
DEVICE
97h
85h
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
UVEPROM
Austin Semiconductor, Inc.
READ/OUTPUT DISABLE
When the outputs of two or more SMJ27C512 are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from
competing outputs of the other devices. To read the output of
the selected SMJ27C512, a low-level signal is applied to the
E\ and G\ /V
PP
. All other devices in the circuit should have
their outputs disabled by applying a high-level signal to one of
these pins. Output data is accessed at pins DQ0 through DQ7.
SMJ27C512
SNAP! PULSE PROGRAMMING
The SMJ27C512 is programmed using the SNAP! Pulse
programming algorithm as illustrated by the flowchart in
Figure 1. This algorithm programs in a nominal time of seven
seconds. Actual programming time varies as a function of the
programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed. The SNAP!
Pulse programming algorithm uses an initial pulse of 100µs
followed by a byte verification to determine when the addressed
byte has been successfully programmed. Up to ten 100µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when G\ /V
PP
= 13V,
V
CC
= 6.5V, and E\ = V
IL
. More than one device can be
programmed when the devices are connected in parallel.
Locations can be programmed in any order. When the SNAP!
Pulse programming routine is complete, all bits are verified
with V
CC
= 5V, G\ /V
PP
= V
IL
, and E\ = V
IL
.
LATCHUP IMMUNITY
Latchup immunity on the SMJ27C512 is a minimum of 250mA
on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the EPROM is interfaced to
industry-standard TTL or MOS logic devices. Input/output
layout approach controls latchup without compromising
performance or packing density.
POWER DOWN
Active I
CC
supply current can be reduced from 35mA to
500µA(TTL-level inputs) or 300µA (CMOS-level inputs) by
applying a high TTL/CMOS signal to the E\ pin. In this mode
all outputs are in the high-impedance state.
PROGRAM INHIBIT
Programming can be inhibited by maintaining high level
input on E\.
ERASURE
Before programming, the SMJ27512 is erased by exposing
the chip through the transparent lid to a high-intensity ultra-
violet (UV) light (wavelength 2537 Å). EPROM erasure
before programming is necessary to assure that all bits are in
the logic-high state. Logic lows are programmed into the
desired locations. A programmed logic low can be erased
only by ultraviolet light. The recommended minimum
exposure dose (UV intensity x exposure time) is 15 W
.
s/cm
2
.
A typical 12mW/cm
2
, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5cm above
the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains
the
correct wavelength for erasure; therefore, when using
the SMJ27C512, the window should be covered with an opaque
label.
PROGRAM VERIFY
Programmed bits can be verified with G\ /V
PP
and E\ = V
IL
.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and device type. This mode is
activated when A9 (terminal 24) is forced to 12V ±0.5V. Two
identifier bytes are accessed by A0 (terminal 10); i.e.,
A0 = V
IL
accesses the manufacturer code, which is output on
DQ0-DQ7; A0 = V
IH
accesses the device code, which is also
output on DQ0-DQ7. All other addresses must be held at V
IL
.
Each byte possesses odd parity on bit DQ7. The
manufacturer code for these devices is 97h and the device
code is 85h.
SMJ27512
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
UVEPROM
Austin Semiconductor, Inc.
SMJ27C512
FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART
START
Address = First Location
V
CC
= 6.5V ± 0.25V, G\ /V
PP
= 13V ± 0.25V
Program One Pulse = t
W
= 100µs
Increment Address
Program
Mode
Last
Address?
No
Yes
Address = First Location
X=0
Program One Pulse = t
W
= 100µs
No
Verify
Word
Increment
Address
Fail
X = X+1
X = 10?
Pass
Last
Address?
Interactive
Mode
No
Yes
V
CC
= 5V ± 0.5V, G\ /V
PP
= V
IL
Yes
Device Failed
Compare
All Bytes
to Original
Data
Fail
Final
Verification
Pass
Device Passed
SMJ27512
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
UVEPROM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range, V
CC
**...........................-0.6V to +7.0V
Supply Voltage Range, V
pp
**.........................-0.6V to +14.0V
Input Voltage Range, All inputs except A9
**
....-0.6V to 6.5V
A9....-0.6V to +13.5V
Output Voltage Range**...............................-0.6V to V
CC
+1V
Operating Cage Temperature Range, T
C
.........-55°C to 125°C
Storage Temperature Range, T
stg
.....................-65°C to 150°C
SMJ27C512
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
** All voltage values are with respect to GND.
RECOMMENDED OPERATING CONDITIONS
V
CC
Supply Voltage
1
G\ /V
PP
Supply Voltage
2
Voltage level on A9 for signature mode
V
ID
V
IH
V
IL
T
C
High-level DC input voltage
Low-level DC input voltage
Operating case temperature
Read Mode
SNAP! Pulse programming algorithm
SNAP! Pulse programming algorithm
MIN
4.5
6.25
12.75
11.5
NOM
5
6.5
13
MAX
5.5
6.75
13.25
12.5
V
CC
+1
V
CC
+1
0.8
0.2
125
UNIT
V
V
V
V
V
V
V
V
°C
TTL
CMOS
TTL
CMOS
2
V
CC
-0.2
-0.5
-0.5
-55
NOTES:
1. V
CC
must be applied before or at the same time as G\ /V
PP
and removed after or at the same time as G\ /V
PP
. The deivce must not be inserted into or removed
from the board when G\ /V
PP
or V
CC
is applied.
2. G\ /V
PP
can be connected to V
CC
directly (except in the program mode). V
CC
supply current in this case is I
CC
+ I
PP
.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
OPERATING CONDITIONS
V
OH
V
OL
I
I
I
O
I
PP
I
CC1
PARAMETER
High-level output voltage
Low-level output voltage
Input current (leakage)
Output current (leakage)
G\ /V
PP
supply current (during program pulse)
V
CC
supply current (standby)
2
TEST CONDITIONS
I
OH
= -400µA
I
OL
= 2.1mA
V
I
= 0V to 5.5V
V
O
= 0V to V
CC
G\ /V
PP
= 13V
V
CC
= 5.5V, E\=V
IH
E\=V
IL
, V
CC
=5.5V
MIN
2.4
TYP
1
MAX
0.4
10
10
35
70
500
325
TTL-Input Level
CMOS-Input Level V
CC
= 5.5V, E\=V
CC
t
cycle
= minimum cycle time,
outputs open
35
I
CC2
V
CC
supply current (active)
50
NOTES:
1. Typical values are at T
C
=25°C and nominal voltages.
2. This parameter has been characterized at 25°C and is not production tested.
SMJ27512
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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