EEWORLDEEWORLDEEWORLD

Part Number

Search

550ME166M628DGR

Description
VCXO; DIFF/SE; SINGLE FREQ; 10-1
CategoryPassive components    oscillator   
File Size458KB,15 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

550ME166M628DGR Online Shopping

Suppliers Part Number Price MOQ In stock  
550ME166M628DGR - - View Buy Now

550ME166M628DGR Overview

VCXO; DIFF/SE; SINGLE FREQ; 10-1

550ME166M628DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT PACKAGE-6
Reach Compliance Codecompliant
Other featuresCOMPLEMENTARY OUTPUT; TRI-STATE; ENABLE/DISABLE FUNCTION; TAPE AND REEL
Maximum control voltage3.3 V
Minimum control voltage
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate25 ppm
frequency stability20%
JESD-609 codee4
linearity10%
Manufacturer's serial numberSI550
Installation featuresSURFACE MOUNT
Number of terminals6
Maximum operating frequency1417 MHz
Minimum operating frequency10 MHz
Nominal operating frequency166.628 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
Package body materialPLASTIC/EPOXY
Encapsulate equivalent codeDILCC6,.2
physical size7.0mm x 5.0mm x 1.85mm
power supply3.3 V
Certification statusNot Qualified
longest rise time0.35 ns
Maximum slew rate130 mA
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Si550
R
EVISION
D
V
O L TAG E
- C
ONTR OLLED
C
RYSTAL
O
S C I L L A T O R
(VCXO)
10 MH
Z TO
1 . 4 G H
Z
Features
Available with any frequency from
10 to 945 MHz and select
frequencies to 1.4 GHz
3rd generation DSPLL
®
with
superior jitter performance (0.5 ps)
3x better temperature stability than
SAW-based oscillators
Excellent PSRR performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 10.
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Pin Assignments:
See page 9.
(Top View)
V
C
1
2
3
6
5
4
V
DD
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 supports any
frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si550 uses one fixed crystal to provide a wide range of output
frequencies. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems. The Si550 IC-based VCXO is factory-configurable
for a wide variety of user specifications, including frequency, supply voltage,
output format, tuning slope, and temperature stability. Specific configurations
are factory programmed at time of shipment, thereby eliminating the long
lead times associated with custom oscillators.
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
Fixed
Frequency
XO
Any-Frequency
10 MHz–1.4 GHz
DSPLL
®
Clock Synthesis
CLK+
CLK–
Vc
ADC
OE
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si550
The download and win gift event is here again~you can learn and win prizes at the same time!
Learn and win awards at the same timeLet’s keep it simple and get straight to the point!Event time: From now until October 31, 2019Activity process: 1. Open theBuild a healthy life, achieve powerful t...
EEWORLD社区 Integrated technical exchanges
Laser Receiver Project
Has anyone made a laser receiver? The receiver is a 5~10KHz red laser using silicon photocells. I have the schematic diagram of the prototype and I have tuned the board, but I don't know how to collec...
liuzhouhu Embedded System
Several macros in DE1-SoC
What are the specific meanings of these macros HW_REGS_BASE(ALT_STM_OFST) HW_REGS_SPAN ALT_LWFPGASLVS_OFST?...
全部都是泡馍 FPGA/CPLD
Why is it said that the larger the ceramic capacitor package, the better the frequency characteristics?
[size=4]When the frequency is constant, the larger the capacitance, the smaller the capacitive reactance; the smaller the capacitive reactance, the lower the frequency that passes. [/size] [size=4]The...
fish001 Analogue and Mixed Signal
Selecting Switching Power Supply Core Size and Type Based on Experience
This is a document that provides information on selecting the size and type of the switching power supply core based on experience. You can refer to it. [url]https://download.eeworld.com.cn/download/1...
快羊加鞭 Download Centre

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2847  1275  2391  2127  1218  58  26  49  43  25 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号