552AJ000177DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 552AJ000177DG

552AJ000177DG: DescriptionVCXO; DIFF/SE; DUAL FREQ; 10-141; CategoryPassive components oscillator; File Size477KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

552AJ000177DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	552AJ000177DG	-	-	View	Buy Now

552AJ000177DG Overview

VCXO; DIFF/SE; DUAL FREQ; 10-141

552AJ000177DG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	DILCC6,.2
Reach Compliance Code	compliant
Installation features	SURFACE MOUNT
Number of terminals	6
Maximum operating frequency	945 MHz
Minimum operating frequency	10 MHz
Nominal operating frequency	657.42188 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
Encapsulate equivalent code	DILCC6,.2
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	130 mA
Nominal supply voltage	3.3 V
surface mount	YES

Preview

Download Datasheet

View All

Si 5 5 2

EVISION

U A L

REQUENCY

OLTAGE

- C

ON TROLLED

R Y S TA L

SCILLATOR

(VCXO) 10 MH

Z TO

1 . 4 G H

Features

Available with any-rate output

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz



Two selectable output frequencies



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than

SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications

SONET/SDH



xDSL



10 GbE LAN/WAN



Ordering Information:

Low-jitter clock generation



Optical modules



Clock and data recovery



See page 10.

Description

The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low-jitter clocks in noisy environments typically found in communication

systems. The Si552 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

Pin Assignments:

See page 9.

(Top View)

GND

CLK–

CLK+

Functional Block Diagram

CLK- CLK+

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 1.2 6/18

Si552

Recommended Resources

Blood pressure detector display circuit

Machine tool maintenance bearing fault detection circuit

SaSong brand BCD-170W refrigerator circuit

Household thermostat circuit

AND gate control circuit

1-50kHz sine wave oscillation circuit

Ask for advice on BCD BIN command data conversion format: Dear experts, I am confused by these two instructions. Please tell me how the data in these two instructions are converted. My understanding is: BIN: For example, the keyboard input is 528400. To ente...; eeleader Industrial Control Electronics

There are breakpoint issues encountered in AXD and MULTIICE simulations: I have a board connected to MULIICESERVER. The BIOS has been burned into the NORFLASH of the board. I am using AXD to debug. I used LOAD to download the debug image .AXF file into the board. Why can I...; yaowenqiang Embedded System

LPC11C14 chip uart receiving interrupt problem: I use Uart serial port interrupt mode to receive data on LPC11C14 chip. The FIFO interrupt trigger byte number is set to 4 bytes. I use serial port assistant on PC to send 5 characters of "hello". LPC...; xcyhere NXP MCU

How to divide nandflash into two fat areas?: I am currently using a Freescale m31+ce5.0 system. After modifying the hive registry, the 512MB nand flash now has a fat partition, and the nand flash disk can be seen after the system starts. I now w...; dfx168 Embedded System

Experts tell us how to make a good FPGA: Da Xia: I have always wanted to make FPGA. I have read a lot of books, but I am still confused. Because most of them are simple examples, and some are a little more complicated. But I always feel that...; heningbo FPGA/CPLD

EVC connection error.: I copied the printer USB program under PB to a folder. Use EVC4 to create a dll project. And include these CH files and set the path. The compilation and connection errors are as follows: Creating lib...; whbahx Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components