dsPIC33EPXXXGM3XX/6XX/7XX FAMILY
dsPIC33EPXXXGM3XX/6XX/7XX Family
Silicon Errata and Data Sheet Clarification
The dsPIC33EPXXXGM3XX/6XX/7XX family devices
that you have received conform functionally to the
current Device Data Sheet (DS70000689D), except for
the anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of dsPIC33EPXXXGM3XX/6XX/7XX
family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the issues
indicated in the last column of
Table 2
apply to the current silicon revision (A3).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with a hardware debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select
Programmer >
Reconnect.
b) For MPLAB X IDE, select
Window > Dash-
board
and click the
Refresh Debug Tool
Status
icon (
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
5.
Data Sheet clarifications and corrections start on
Page 25,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The
DEVREV
values
for
the
various
dsPIC33EPXXXGM3XX/6XX/7XX family silicon revisions
are shown in
Table 1.
2013-2018 Microchip Technology Inc.
DS80000577P-page 1
dsPIC33EPXXXGM3XX/6XX/7XX FAMILY
TABLE 1:
SILICON DEVREV VALUES
Part Number
dsPIC33EP128GM304
dsPIC33EP128GM604
dsPIC33EP128GM306
dsPIC33EP128GM706
dsPIC33EP128GM310
dsPIC33EP128GM710
dsPIC33EP256GM304
dsPIC33EP256GM604
dsPIC33EP256GM306
dsPIC33EP256GM706
dsPIC33EP256GM310
dsPIC33EP256GM710
dsPIC33EP512GM304
dsPIC33EP512GM604
dsPIC33EP512GM306
dsPIC33EP512GM706
dsPIC33EP512GM310
dsPIC33EP512GM710
Note 1:
Device ID
0x1B40
0x1B48
0x1B43
0x1B4B
0x1B47
0x1B4F
0x1B80
0x1B88
0x1B83
0x1B8B
0x1B87
0x1B8F
0x1BC0
0x1BC8
0x1BC3
0x1BCB
0x1BC7
0x1BCF
0x4000
0x4001
0x4002
0x4003
(1)
Revision ID for Silicon Revision
(2)
A0
A1
A2
A3
2:
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of
configuration memory space. They are shown in hexadecimal in the format “DEVID
DEVREV”.
Refer to the
“dsPIC33EPXXXGM3XX/6XX/7XX Flash Programming Specification”
(DS70000685) for detailed information on Device and Revision IDs for your specific device.
DS80000577P-page 2
2013-2018 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX FAMILY
TABLE 2:
Module
Core
Core
SPI
SPI
Input Capture
PWM
SILICON ISSUE SUMMARY
Feature
CPU
Program
Memory
Frame Sync
Pulse
Frame Master
Mode
Synchronous
Cascade mode
Immediate
Update
PWM Override
Item
Number
1.
2.
3.
4.
5.
6.
Issue Summary
Limited execution speed (44/64-pin and 100/121-pin
devices).
The address error trap may occur while accessing
certain program memory locations.
When in SPIx Slave mode with the Frame Sync
pulse set as an input, FRMDLY must be set to ‘0’.
Received data is right-shifted under certain
conditions.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
Revisions
(1)
A0 A1 A2 A3
Even numbered timer does not reset on a source
X
clock rollover in a synchronous cascaded operation.
Dead time is not asserted when PDCx is updated to
cause an immediate transition on the PWMxH and
PWMxL outputs.
Under certain circumstances, updates to the
OVRENH and OVRENL bits may be ignored by the
PWMx module.
With dead time greater than zero, 0% and 100%
duty cycles cannot be obtained on PWMxL and
PWMxH outputs.
Under certain conditions, the PWMxH and PWMxL
outputs are deasserted.
PWM Resets only occur on alternate cycles in
Current Reset mode.
When the Immediate Update is disabled, certain
changes to the PHASEx register may result in
missing dead time.
When the Immediate Update is disabled, changing
the duty cycle value from a non-zero value to zero
will produce a glitch pulse equal to 1 PWM clock.
If PWM override is turned off during dead time, then
the PWM generator may not provide dead time on
the corresponding PWMxH-PWMxL edge transition.
DONE bit does not work when an external interrupt
is selected as the ADC trigger source.
Selecting the same ANx input for CH0 and CH1
results in erroneous readings for CH1.
Write collisions on a DMA-enabled CAN module do
not generate DMAC error traps.
MCLR pin operation may be disabled.
Active-high logic pulse on the I/O pin with TMS
function at POR.
Under certain circumstances, the Velocity Counter x
register (VELxCNT) misses count pulses.
Change in the FRC accuracy.
X
PWM
7.
X
X
PWM
Complementary
Mode
Center-Aligned
Mode
Current Reset
Mode
Master Time
Base Mode
Redundant/
Push-Pull
Output Mode
Complementary
Mode
DONE bit
Analog Channel
DMA
I/O
I/O
Velocity Counter
FRC Accuracy
8.
X
X
X
X
PWM
PWM
PWM
9.
10.
11.
X
X
X
X
X
X
X
X
X
X
X
X
PWM
12.
X
X
X
X
PWM
13.
X
X
X
X
ADC
ADC
CAN
JTAG
JTAG
QEI
FRC
Note 1:
14.
15.
16.
17.
18.
19.
20.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
2013-2018 Microchip Technology Inc.
DS80000577P-page 3
dsPIC33EPXXXGM3XX/6XX/7XX FAMILY
TABLE 2:
Module
Op Amp
CPU
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Op Amp Offset
Voltage
div.sd
Item
Number
21.
22.
Issue Summary
Drift in the op amp offset voltage.
When using the signed 32-by-16-bit division
instruction,
div.sd,
the Overflow bit is not getting
set when an overflow occurs.
In the scaled down timer source for the Output
Compare module, the first PWM pulse may not
appear on the OCx pin.
Under certain circumstances, an Output Compare
match may cause the Output Compare x Interrupt
Flag (OCxIF) bit to become set prior to the
Change-of-State (COS) of the OCx pin.
PSV access, including Table Reads or Writes in the
first or last instruction of a
DO
loop, is not allowed.
In Center-Aligned mode, there is missing dead time
when SWAP is disabled.
Updates to the PHASEx registers occur only at the
middle of the center-aligned PWM cycle.
The AC/DC electrical characteristic, Integral
Nonlinearity error in the ADC module, is not within
the specifications published in the data sheet.
Period register writes may produce back-to-back
pulses under certain conditions.
First PWM/ADC trigger event on TRIGx match may
not occur under certain conditions.
When IC is used in Cascaded mode, the even timer
does not increment immediately when the odd timer
rolls over, but instead occurs one cycle after the
rollover.
The data transferred from DMA to the SPIx buffer
may get corrupted if the CPU accesses the Special
Function Registers (SFRs) during the data transfer.
DO
loops may work incorrectly if nested interrupts
are enabled and interrupts occur during the last two
instructions of the
DO
loop.
Address error trap may occur under certain
circumstances if Variable Interrupt Latency mode is
enabled.
Stack error trap may occur under certain
circumstances if the processor is
switched between normal mode and Doze mode.
When the SPIx module is enabled for the first time,
there may be a spurious clock on the SCKx pin,
which causes a mismatch between the clock and
data lines.
X
X
Affected
Revisions
(1)
A0 A1 A2 A3
X
X
X
X
X
X
Output Compare
PWM Mode
23.
X
X
X
X
Output Compare
Interrupt
24.
X
X
X
X
CPU
PWM
PWM
ADC
DO
Loop
PWM SWAP
Center-Aligned
Mode
Integral
Nonlinearity (INL)
Specification
Push-Pull Mode
Trigger Compare
Match
Cascade Mode
25.
26.
27.
28.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PWM
PWM
Input Capture
29.
30.
31.
X
X
X
X
X
X
X
X
X
X
X
X
SPI
DMA
32.
X
X
X
X
Core
DO
Loop
33.
X
X
X
X
Core
Variable Interrupt
Latency
Doze Mode
34.
X
X
X
X
Power-Saving
Mode
SPI
35.
X
X
X
X
SPIx Enable
36.
X
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80000577P-page 4
2013-2018 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX FAMILY
TABLE 2:
Module
Data Memory
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Stack Error Trap
Item
Number
37.
Issue Summary
If the CPU is assigned a lower data bus master
priority level than either the DMA Controller or USB,
by configuring the MSTRPR register to any value
other than 0x0000, then executing an
ULNK
instruction will result in a stack error trap.
Received data is shifted by 1 bit when CKP =
1
and
CKE =
0.
Single-stepping of the command sequence queue
when device is in Debug mode is not functional.
PTGADD
and
PTGCOPY
commands do not change
the counter limit values.
Schmitt Trigger output may produce glitches.
Given a specific set of preconditions, when two or
more data Flash read instructions (via Program
Space Visibility (PSV) read or table read) are
executed back-to-back, one or more subsequent
instructions will be misexecuted.
ADC2 module specifications Parameters AD23a and
HAD23a Gain Error (GERR) are updated to ±15%.
X
Affected
Revisions
(1)
A0 A1 A2 A3
X
X
X
SPI
PTG
PTG
I/O
CPU
Master Mode
Debug Mode
PTGADD/
PTGCOPY
Schmitt Trigger
Data Flash
Reads
38.
39.
40.
41.
42.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Electrical
Characteristics
Note 1:
ADC2 Gain error
43.
X
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
2013-2018 Microchip Technology Inc.
DS80000577P-page 5
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