FEDD56V16160K-01
Issue Date : Oct. 19, 2010
MSM56V16160K
2-Bank×524,288-Word×16-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MSM56V16160K is a 2-Bank
×
524,288-word
×
16-bit Synchronous dynamic RAM. The device
operates at 3.3V. The inputs and outputs are LVTTL compatible.
FEATURES
Product Name
Organization
Address Size
Power Supply VCC (Core)
Power Supply VCCQ (I/O)
Interface
Operating Frequency
Operating Temperature
/CAS Latency
Burst Length
Burst Type
Write Mode
Refresh
Package
MSM56V16160K
2Bank x 524,288Word x 16Bit
2,048Row x 256Column
3.3V±0.3V
3.3V±0.3V
LVTTL compatible
Max. 125MHz (Speed Rank 8)
0 to 70°C
2, 3
1, 2, 4, 8, Full page
Sequential, Interleave
Burst, Single
Auto-Refresh, 4,096cycle/64ms, Self-Refresh
50-Pin Plastic TSOP(II) (Cu frame)
(P-TSOPII50-P-400-0.80-ZK)
PRODUCT FAMILY
Access Time (Max.)
tAC2
6ns
6ns
tAC3
6ns
6ns
Family
MSM56V16160K-8
MSM56V16160K-10
Max. Frequency
125MHz
100MHz
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FEDD56V16160K-01
MSM56V16160K
PIN CONFIGURATION (TOP VIEW)
50-Pin Plastic TSOP(II)
1
2
3
4
5
6
VCCQ 7
DQ4 8
DQ5 9
V
SS
Q 10
DQ6 11
DQ7 12
V
CC
Q 13
LDQM 14
/WE 15
/CAS 16
/RAS 17
/CS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VCC 25
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VCCQ
DQ11
DQ10
VSSQ
DQ9
DQ8
38 VCCQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
50
49
48
47
46
45
44
43
42
41
40
Pin Name
CLK
/CS
CKE
A0–A10
A11
/RAS
/CAS
/WE
Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
UDQM, LDQM
DQi
VCC
VSS
VCCQ
VSSQ
NC
Function
Data Input / Output Mask
Data Input / Output
Power Supply (3.3V)
Ground (0V)
Data Output Power Supply (3.3V)
Data Output Ground (0V)
No Connection
Note : The same power supply voltage must be provided to every VCC pin .
The same power supply voltage must be provided to every VCCQ pin.
The same GND voltage level must be provided to every VSS pin and VSSQ pin.
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FEDD56V16160K-01
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PIN DESCRIPTION
CLK
Clock (Input)
Fetches all inputs at the “H” edge.
Clock Enable (Input)
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Chip Select (Input)
/CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE
and UDQM, LDQM.
Row Address Strobe (Input)
/RAS
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Column Address Strobe (Input)
/CAS
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Write Enable (Input)
/WE
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Bank Address (Input)
A11
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
Row & column multiplexed. (Input)
Row address
: RA0 – RA10
Column Address
: CA0 – CA7
3-state Data Bus (Input/Output)
DQ Mask (Input)
UDQM, LDQM
Masks the read data of two clocks later when DQM are set “H” at the “H” edge of the clock
signal. Masks the write data of the same clock when DQM are set “H” at the “H” edge of the
clock signal. UDQM controls DQ15 to DQ8, LDQM controls DQ7 to DQ0.
Power Supply (Core), Ground (Core)
VCC, VSS
The same power supply voltage must be provided to every VCC pin.
The same GND voltage level must be provided to every VSS pin.
Power Supply (I/O), Ground (I/O)
VCCQ, VSSQ
The same power supply voltage must be provided to every VCCQ pin.
The same GND voltage level must be provided to every VSSQ pin.
NC
No Connection
A10 to A0
DQ15 to DQ0
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MSM56V16160K
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Input/Output Pin Relative to VSS
VCC Supply Voltage
VCCQ Supply Voltage
Power Dissipation (Ta=25°C)
Short Circuit Output Current
Storage Temperature
Operating Temperature
Symbol
VIN, VOUT
VCC
VCCQ
PD
IOS
Tstg
Topr
Value
–0.5 to VCC+0.5
–0.5 to 4.6
–0.5 to 4.6
1000
50
–55 to 150
0 to 70
Unit
V
V
V
mW
mA
°C
°C
Notes: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
2. Functional operation should be restricted to recommended operating condition.
3. Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
Recommended Operating Conditions (1/2)
Voltages referenced to VSS = 0 V
Parameter
Power Supply Voltage (Core)
Power Supply Voltage (I/O)
Ground
Symbol
VCC
VCCQ
VSS, VSSQ
Min.
3.0
3.0
0
Typ.
3.3
3.3
0
Max.
3.6
3.6
0
Unit
V
V
V
Note
1
1
Notes: 1. The voltages are referenced to VSS
Recommended Operating Conditions (2/2)
Ta= 0 to 70°C
Parameter
Input High Voltage
Input Low Voltage
Symbol
VIH
VIL
Min.
2.0
−0.3
Max.
VCC + 0.2
0.8
Unit
V
V
Note
1, 2
1, 3
Notes: 1. The voltages are referenced to VSS.
2. The input voltage is VCC + 0.5V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
3. The input voltage is
−
0.5V when the pulse width is less than 20ns (the pulse width respect to the point at
which VSS and VSSQ are applied).
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Pin Capacitance
Ta = 25°C, VCC＝VCCQ＝3.3V, f＝1MHz
Parameter
Input Capacitance (CLK)
Input Capacitance
(A0 – A11, /RAS, /CAS, /WE, /CS, CKE, UDQM, LDQM)
Input/Output Capacitance (DQ15 – DQ0)
Symbol
CCLK
CIN
COUT
Min.
Max.
4
5
6.5
Unit
pF
pF
pF
DC Characteristics (Input/Output)
Ta = 0 to 70°C
VCC = VCCQ = 3.3V±0.3V
Max.
Unit
0.4
10
10
V
V
A
A
Parameter
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Symbol
VOH
VOL
ILI
ILO
Condition
IOH =
−0.2mA
IOL = 0.2mA
0V VIN VCCQ
Min.
2.4
−10
−10
Note : The voltages are referenced to VSS.
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