LPC11Axx
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB
SRAM, 4 kB EEPROM; configurable analog/mixed-signal
Rev. 4 — 30 October 2012
Product data sheet
1. General description
The LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11Axx operate at CPU frequencies of up to 50 MHz.
Analog/mixed-signal subsystems can be configured by software from interconnected
digital and analog peripherals.
The digital peripherals on the LPC11Axx include up to 32 kB of flash memory, up to 4 kB
of EEPROM data memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I
2
C-bus
interface, a RS-485/EIA-485 USART, two SSP controllers, four general purpose
counter/timers, and up to 42 general purpose I/O pins.
Analog peripherals include a 10-bit ADC, a 10-bit DAC, an analog comparator, a
temperature sensor, an internal voltage reference, and UnderVoltage LockOut (UVLO)
protection.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug (SWD)
JTAG boundary scan.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
Up to 8 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) for flash and In-Application Programming (IAP) for
flash and EEPROM via on-chip bootloader software.
Includes ROM-based 32-bit integer division and I
2
C-bus driver routines.
Digital peripherals:
Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
NXP Semiconductors
LPC11Axx
32-bit ARM Cortex-M0 microcontroller
LPC11AXX
Up to 16 pins are configurable with a digital input glitch filter for removing glitches
with widths of 10 ns or less and two pins are configurable for 50 ns glitch filters.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current source output driver (20 mA) on one pin (PIO0_21).
High-current sink driver (20 mA) on true open-drain pins (PIO0_2 and PIO0_3).
Four general purpose counter/timers with a total of up to 16 capture inputs and 14
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDOsc).
Analog peripherals:
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC with flexible conversion triggering.
Highly flexible analog comparator with a programmable voltage reference.
Integrated temperature sensor.
Internal voltage reference.
UnderVoltage Lockout (UVLO) protection against power-supply droop below 2.4 V.
Serial interfaces:
USART with fractional baud rate generation, internal FIFO, support for
RS-485/9-bit mode and synchronous mode.
Two SSP controllers with FIFO and multi-protocol capabilities. Support data rates
of up to 25 Mbit/s.
I
2
C-bus interface supporting the full I
2
C-bus specification and Fast-mode Plus with
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC Oscillator (IRC) trimmed to 1% accuracy that can optionally be
used as a system clock.
Internal low-power, Low-Frequency Oscillator (LFOsc) with programmable
frequency output.
Clock input for external system clock (25 MHz typical).
PLL allows CPU operation up to the maximum CPU rate with the IRC, the external
clock, or the SysOsc as clock sources.
Clock output function with divider that can reflect the SysOsc, the IRC, the main
clock, or the LFOsc.
Power control:
Supports one reduced power mode: The ARM Sleep mode.
Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
Processor wake-up from reduced power mode using any interrupt.
Power-On Reset (POR).
Brown-Out Detect (BOD) with two programmable thresholds for interrupt and one
hardware controlled reset trip point.
POR and BOD are always enabled for rapid UVLO protection against power supply
voltage droop below 2.4 V.
Unique device serial number for identification.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
2 of 84
NXP Semiconductors
LPC11Axx
32-bit ARM Cortex-M0 microcontroller
Single 3.3 V power supply (2.6 V to 3.6 V).
Temperature range
40 C
to +85
C.
Available as LQFP48 package, HVQFN33 (
7
7
) and HVQFN33 (
5
5
) packages, and
in a very small WLCSP20 package.
3. Applications
Power management
Industrial control
Remote monitoring
Point-of-sale
Test and measurement equipment
Network appliances and services
Factory automation
Gaming equipment
Motion control
Medical instrumentation
Fire and security
Sensors
Precision instrumentation
HVAC and building control
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC11A02UK
LPC11A04UK
Description
Version
-
-
WLCSP20 wafer level chip-size package; 20 bumps; 2.5
2.5
0.6 mm
WLCSP20 wafer level chip-size package; 20 bumps; 2.5
2.5
0.6 mm
Type number
LPC11A11FHN33/001 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7
7
0.85 mm
LPC11A12FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7
7
0.85 mm
LPC11A13FHI33/201
HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 5
5
0.85 mm
LPC11A14FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7
7
0.85 mm
LPC11A12FBD48/101 LQFP48
LPC11A14FBD48/301 LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
SOT313-2
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
3 of 84
NXP Semiconductors
LPC11Axx
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
Table 2.
Ordering options
10-bit ADC channels
Temperature sensor
Analog comparator
Flash
SRAM
EEPROM
Package
Type number
10-bit DAC
SSP/SPI
USART
LPC11A02UK
LPC11A04UK
LPC11A11FHN33/001
LPC11A12FHN33/101
LPC11A12FBD48/101
LPC11A13FHI33/201
LPC11A14FHN33/301
LPC11A14FBD48/301
16 kB
32 kB
8 kB
16 kB
16 kB
24 kB
32 kB
32 kB
4 kB
8 kB
2 kB
4 kB
4 kB
6 kB
8 kB
8 kB
2 kB
4 kB
512 B
1 kB
1 kB
2 kB
4 kB
4 kB
8
8
8
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
18
18
28
28
42
28
28
42
GPIO
WLCSP20
WLCSP20
HVQFN33
HVQFN33
LQFP48
HVQFN33
HVQFN33
LQFP48
© NXP B.V. 2012. All rights reserved.
LPC11AXX
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 4 — 30 October 2012
I
2
C
4 of 84
NXP Semiconductors
LPC11Axx
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD
XTALIN XTALOUT
RESET
LPC11Axx
TEST/DEBUG
INTERFACE
SysOsc
(3)
IRC, LFOSC, WDOSC
BOD
EEPROM
512 B/
1/4 kB
FLASH
8/16/24/32 kB
slave
POR
clocks, internal voltage reference,
and controls
SRAM
2/4/6/8 kB
slave
ROM
16 kB
slave
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
CLKOUT
CLKIN
ARM
CORTEX-M0
system bus
GPIO ports
HIGH-SPEED
GPIO
slave
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
USART
(4)
10-bit ADC
AD[7:0]
ATRG[1:0]
RXD
TXD
CTS, DCD, DSR, RI
RTS, DTR
SCLK
CT32B0_MAT[3:0]
CT32B0_CAP[2:0]
CT32B1_MAT[3:0]
CT32B1_CAP[2:0]
CT16B0_MAT[3:0]
CT16B0_CAP[2:0]
CT16B1_MAT[3:0]
CT16B1_CAP[2:0]
TEMPERATURE SENSOR
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
WINDOWED WATCHDOG
TIMER
PMU
SYSTEM CONTROL
SSP0
SSP1
(3)
SCK0, SSEL0,
MISO0, MOSI0
SCK1, SSEL1,
MISO1, MOSI1
I
2
C-BUS
IOCONFIG
SCL, SDA
(1)
SCL, SDA
(2)
SCL, SDA
(2)
SCL, SDA
(2)
ANALOG COMPARATOR
ACMP_I[5:1]
ACMP_O
VDDCMP
AOUT
10-bit DAC
002aaf428
(1) Open-drain pins.
(2) Standard I/O pins.
(3) Not available on WLCSP packages.
(4) Modem control pins not available on WLCSP packages.
Fig 1.
LPC11Axx block diagram
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
5 of 84
京公网安备 11010802033920号
EEWORLD
