MicroClock Programmable Clock
Generator
Datasheet
5X2503
Description
The 5X2503 MicroClock is a programmable clock generator and is
intended for low-power, consumer, wearable and smart devices.
The 5X2503 device is a 3 PLL architecture design. Each PLL is
individually programmable, allowing for up to 3 unique frequency
outputs. The 5X2503 has built-in unique features such as Proactive
Power Saving (PPS) to deliver better system-level power
management.
An internal OTP memory allows the user to store the configuration in
the device without programming after power up. It can then be
reprogrammed again through the I
2
C interface.
The device has programmable VCO and PLL source selection
allowing the user to do power-performance optimization based on
the application requirements. A low-power 32.768kHz clock is
supported with only less than 2μA current consumption for system
RTC reference clock needs.
Features
▪
Configurable OE1 pin function as OE, PPS or DFC control
function
▪
PPS: Proactive Power Saving features save power during the end
device power-down mode
▪
DFC: Dynamic Frequency Control feature allows programming up
to 4 difference frequencies that switch dynamically
▪
Integrated 26MHz crystal; no external input source requirement
▪
Spread spectrum clock support to lower system EMI
▪
I
2
C Interface
Output Features
▪
3 LVCMOS outputs, 1MHz–125MHz
▪
Low-power 32.768kHz clock supported
▪
Wireless clock crystal integration and fan-out directly
Typical Applications
▪
SmartDevice, Handheld, Wearable applications
▪
Consumer application crystal replacement
Key Specifications
▪
2μA operation for RTC clock 32.768kHz output
▪
2.5 × 2.5 mm 12-DFN with crystal integration; small-form-factor
package
Block Diagram
Power
Monitor
POR
PLL1
OSC
PLL2
Calibration
PLL3
32.768K
DCO
Mux
&
Divider
OE1
OUT1
VDDOUT1
VSS
OUT2
VDDOUT2
VSS
OUT3
VDD1_8
VSS
SEL_DFC/ SCL_DFC1/OE3
SDA_DFC0/OE2
I
2
C Engine
Overshoot Reduction
(ORT)
Dynamic Frequency Control Logic (DFC)
OTP memory (1 configuration )
Proactive Power Saving Logic (PPS)
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5X2503 Datasheet
Power Group
Power Supply
V
DDOUT1
V
DDOUT2
V
DD1_8
SE
OUT1
OUT2/OUT3
DIV
—
—
V
MUX
—
—
V
PLL
—
V
—
DCO
—
—
V
Xtal
—
—
V
Output Source Selection Register Setting Tables
OUT3 Source
Divider 3 (DIV3)
Divider 5 (DIV5)
Divider 1 (DIV1)
32.768kHz DCO
B35b7
0
0
1
1
B35b6
0
1
0
1
OUT2 Source
Divider 3 (DIV3)
Divider 5 (DIV5)
Divider 1 (DIV1)
32.768kHz DCO
OUT2 Source
Divider 3 (DIV3)
Divider 5 (DIV5)
Divider 1 (DIV1)
32.768kHz DCO
DIV1 Source
PLL1
DIV4 seed
B35b5
0
0
1
1
B35b3
0
0
1
1
B35b7
0
1
B35b4
0
1
0
1
B35b2
0
1
0
1
B35b6
0
X
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5X2503 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package
SDA_DFC0/OE2
SEL_DFC/SCL_DFC1/OE3
V
SS
V
SS
V
DD1_8
V
DDOUT1
1
2
3
4
5
6
12
11
10
9
8
7
V
SS
OUT3
V
DDOUT2
OUT2
OE1
OUT1
2.5 × 2.5 mm 12-DFN
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
–
Name
SDA_DFC0/OE2
SEL_DFC/SCL_DFC1/OE3
V
SS
V
SS
V
DD1_8
V
DDOUT1
OUT1
OE1
OUT2
V
DDOUT2
OUT3
V
SS
EPAD
Type
I/O
Input
Power
Power
Power
Power
Output
Input
Output
Power
Output
Power
GND
Description
I
2
C data pin; can be DFC0 function by OTP programming or selected by
SEL_DFC at power-on default. Output enable pin for OUT2.
I
2
C clock pin; can be DFC1 function by OTP programming selected by
SEL_DFC at power-on default. Output enable pin for OUT3.
Ground pin.
Ground pin.
1.8V power rail.
1.2V / 1.8V output clock power supply pin; supports OUT1.
1.2V / 1.8V LVCMOS clock output.
Output enable control 1.
1.8V LVCMOS clock output.
1.8V output clock power supply pin; supports OUT2/3.
1.8V LVCMOS clock output.
Ground pin.
Connect to ground pad.
Device Feature and Function
DFC – Dynamic Frequency Control
▪
OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2.
▪
ORT (overshoot reduction) function will be applied automatically during the VCO frequency change.
▪
Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.
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5X2503 Datasheet
Figure 2. DFC Function Block Diagram
M
M divider
divider
PLL2
PLL2
OUT DIV
DIV
OUT
Selector
Selector
00
01
00
01
N divider
N divider
N divider
N divider
N divider
10
11
DFC1:0
10
11
N divider
N divider
N divider
DFC1:0
OTP/I2C
OTP/I2C
Table 2. DFC Function Priority
DFC Mode
Off
On
On
On
OE Pins
OE In*
DFC0 In
OE In*
OE In*
DFC_EN bit
(W32[4])
0
1
1
1
OE1_fun_sel
00 or 01 or 10*
11
00 or 01 or 10*
00 or 01 or 10*
I
2
C Pins
Active (SCL =
1 at POR)
Active
Inactive (SCL
= 0 at POR)
Active (SCL =
1 at POR)
SCL_DFC1
SCL Input
SCL Input
DFC1
SCL Input
SDA_DFCO
SDA I/O
SDA I/O
DFC0
SDA I/O
DFC[1:0]
N/A
DFC0 = OE
DFC1 =
SCL_DFC1
W30[1:0]
Notes
DFC disable
One pin DFC
via OE1
I
2
C pin as
DFC control
pins
I
2
C control
DFC mode
* See
OE Pin Function
table.
DFC Function Programming
▪
Register B63b3:2 selects DFC00–DFC11 configuration.
▪
Byte16–19 are the registers for PLL2 VCO setting, based on B63b3:2 configuration selection, the data write to B16–19 will be stored in
selected configuration OTP memory.
▪
Refer to
DFC Function Priority
table. Select proper control pin(s) to activate DFC function.
▪
Note the DFC function can also be controlled by I
2
C access.
PPS – Proactive Power Saving Function
PPS (Proactive Power Saving) is an IDT patented unique design for the clock generator that proactively detects end device power down state
and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes < 5μA
current. The system could save power when the device goes into power down or sleep mode. The PPS function diagram is shown as below.
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5X2503 Datasheet
Figure 3. PPS Function Block Diagram
I
2
C
&
Logic
PPS
Control
Logic
Low
Power
DCO
Power
Down
Control
XOUT
XIN
Xtal
Oscillator
Logic
Xtal
Oscillator
PLL
MHz / kHz
Switching
Figure 4. PPS Assertion/Deassertion Timing Chart
3rd cycle
2nd cycle
1st cycle
PPS assertion
MHz clock
32kHz clocks
2nd cycle
1st cycle
PPS deassertion
32kHz clocks
MHz clock
PPS Function Programming
Refer to the
OE Pin Function
table to have proper PPS function selected for OE pin(s). Note that the register default is set to Output Enable
(OE) function for OE pins.
Input Pin Function
The input pins in 5X2503 have multiple functions. The OE1 pin can be configured as output enable control (OE) or chip power-down control
(PD#) or Proactive Power Saving function (PPS). Furthermore, the OE1 pin can be configured as single or Dynamic Frequency Control (DFC).
©2017 Integrated Device Technology, Inc
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December 18, 2017
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