XC4VFX60-11FF672C datasheet, PDF

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XC4VFX60-11FF672C: DescriptionField Programmable Gate Array, 6320 CLBs, 1181MHz, 56880-Cell, CMOS, PBGA672, FBGA-672; File Size5MB，406 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC4VFX60-11FF672C Overview

Field Programmable Gate Array, 6320 CLBs, 1181MHz, 56880-Cell, CMOS, PBGA672, FBGA-672

XC4VFX60-11FF672C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	2032571966
Parts packaging code	BGA
package instruction	FBGA-672
Contacts	672
Reach Compliance Code	not_compliant
Country Of Origin	Taiwan
ECCN code	3A991.D
Factory Lead Time	52 weeks
Samacsys Manufacturer	XILINX
Samacsys Modified On	2023-03-29 09:42:01
YTEOL	3.9
maximum clock frequency	1181 MHz
JESD-30 code	S-PBGA-B672
JESD-609 code	e0
length	27 mm
Humidity sensitivity level	4
Configurable number of logic blocks	6320
Number of entries	352
Number of logical units	56880
Output times	352
Number of terminals	672
Maximum operating temperature	85 °C
Minimum operating temperature
organize	6320 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA672,26X26,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	220
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	27 mm

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Virtex-4 FPGA

User Guide

UG070 (v2.6) December 1, 2008

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,

without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves

the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors

contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with

technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER

WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY

RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL

DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All

other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

08/02/04

09/10/04

Version

1.0

1.1

Revision

Initial Xilinx release. Printed Handbook version.

Chapter 1, “Clock Resources”:

Removed Table 1-6: "BUFGMUX_VIRTEX4 Attributes". Updated

Table 1-1, Table 1-2,

Table 1-5,

the new

Table 1-6.

Revised

Figure 1-2, Figure 1-5, Figure 1-6, Figure 1-7,

Figure 1-9, Figure 1-10, Figure 1-13, Figure 1-14,

and

Figure 1-16.

Associated text around

these tables and figures were revised.

Chapter 2, “Digital Clock Managers (DCMs)”,

changes to

“FACTORY_JF Attribute”

and

Table 2-6.

In Chapter 9, “System Monitor”:

Changed in Figure 9-4, Figure 9-5, Figure 9-7, Figure 9-8, Figure 9-9, Figure 9-10, Figure 9-21,

Figure 9-25, Figure 9-26, and Figure 9-27. Changes to the equation in the Temperature Sensor

section. The following tables had changes: Table 9-3, Table 9-5, Table 9-6, Table 9-9, Table 9-

11, Table 9-12, Table 9-14, and Table 9-15. Changes to the entire System Monitor Calibration,

System Monitor VHDL and Verilog Design Example sections.

02/01/05

1.2

Chapter 1, “Clock Resources”,

revised

“Global Clock Buffers”, “Clock Regions”,

and

“Clock Capable I/O”

sections.

Chapter 4, “Block RAM,”

revised

“Reset,” page 151

description and

Table 4-13.

Chapter 6, “SelectIO Resources,”

removed the device configuration section. The

Virtex-4

Configuration Guide

describes this information in detail. Edited

“SSTL (Stub-Series

Terminated Logic),” page 281.

Replaced LVDS_25_DCI with LVDCI_25 in

“Compatible

example:,” page 302.

Added rule “7” to

“DCI in Virtex-4 FPGA Hardware,” page 241.

Added

“Simultaneous Switching Output Limits,” page 306.

Removed Chapter 9: System Monitor.

Virtex-4 FPGA User Guide

www.xilinx.com

UG070 (v2.6) December 1, 2008

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