MT41K128M16JT-107G:K datasheet, PDF

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MT41K128M16JT-107G:K: DescriptionIC DRAM 2G PARALLEL 96FBGA; Categorystorage storage; File Size16MB，221 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT41K128M16JT-107G:K Overview

IC DRAM 2G PARALLEL 96FBGA

MT41K128M16JT-107G:K Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
package instruction	TFBGA,
Reach Compliance Code	compliant
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH; ALSO OPERATES AT 1.5V NOMINAL SUPPLY
JESD-30 code	R-PBGA-B96
JESD-609 code	e1
length	14 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	96
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
organize	128MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.283 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

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2Gb: x4, x8, x16 DDR3L SDRAM

Description

DDR3L SDRAM

MT41K512M4 – 64 Meg x 4 x 8 banks

MT41K256M8 – 32 Meg x 8 x 8 banks

MT41K128M16 – 16 Meg x 16 x 8 banks

Description

The 1.35V DDR3L SDRAM device is a low-voltage ver-

sion of the 1.5V DDR3 SDRAM device. Refer to the

DDR3 (1.5V) SDRAM data sheet specifications when

running in 1.5V compatible mode.

•

Automatic self refresh (ASR)

Write leveling

Multipurpose register

Output driver calibration

Options

• Configuration

– 512 Meg x 4

– 256 Meg x 8

– 128 Meg x 16

• FBGA package (Pb-free) – x4, x8

– 78-ball (8mm x 10.5mm x 1.2mm)

Rev. K

• FBGA package (Pb-free) – x16

– 96-ball (8mm x 14mm x 1.2mm)

Rev. K

• Timing – cycle time

– 1.07ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-1600)

– 1.5ns @ CL = 9 (DDR3-1333)

– 1.875ns @ CL = 7 (DDR3-1066)

• Operating temperature

– Commercial (0°C

≤

+95°C)

– Industrial (–40°C

≤

+95°C)

• Revision

Marking

512M4

256M8

128M16

-107

-125

-15E

-187E

None

Features

•

= V

DDQ

= 1.35V (1.283–1.45V)

Backward-compatible to V

= V

DDQ

= 1.5V ±0.075V

Differential bidirectional data strobe

8n-bit prefetch architecture

Differential clock inputs (CK, CK#)

8 internal banks

Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

Programmable CAS (READ) latency (CL)

Programmable posted CAS additive latency (AL)

Programmable CAS (WRITE) latency (CWL)

Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

Selectable BC4 or BL8 on-the-fly (OTF)

Self refresh mode

of 95°C

– 64ms, 8192-cycle refresh up to 85°C

– 32ms, 8192-cycle refresh at >85°C to 95°C

Self refresh temperature (SRT)

Table 1: Key Timing Parameters

Speed Grade

-107

1, 2, 3

-125

1, 2

-15E

-187E

Notes:

Data Rate (MT/s)

1866

1600

1333

1066

Target

RCD-

RP-CL

13-13-13

11-11-11

9-9-9

7-7-7

RCD

(ns)

CL (ns)

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x4, x8, x16 DDR3L SDRAM

Description

Contents

Important Notes and Warnings ....................................................................................................................... 12

State Diagram ................................................................................................................................................ 13

Functional Description ................................................................................................................................... 14

Industrial Temperature ............................................................................................................................... 14

General Notes ............................................................................................................................................ 14

Functional Block Diagrams ............................................................................................................................. 16

Ball Assignments and Descriptions ................................................................................................................. 18

Package Dimensions ....................................................................................................................................... 24

Electrical Specifications .................................................................................................................................. 26

Thermal Characteristics .................................................................................................................................. 38

Electrical Specifications – I

Specifications and Conditions ............................................................................ 40

Electrical Characteristics – I

Specifications .................................................................................................. 51

Electrical Specifications – DC and AC .............................................................................................................. 52

DC Operating Conditions ........................................................................................................................... 52

Input Operating Conditions ........................................................................................................................ 53

DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 57

DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 61

DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 63

ODT Characteristics ....................................................................................................................................... 64

1.35V ODT Resistors ................................................................................................................................... 65

ODT Sensitivity .......................................................................................................................................... 66

ODT Timing Definitions ............................................................................................................................. 66

Output Driver Impedance ............................................................................................................................... 70

34 Ohm Output Driver Impedance .............................................................................................................. 71

DDR3L 34 Ohm Driver ................................................................................................................................ 72

DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 73

DDR3L Alternative 40 Ohm Driver ............................................................................................................... 74

DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 74

Output Characteristics and Operating Conditions ............................................................................................ 76

Reference Output Load ............................................................................................................................... 79

Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 79

Slew Rate Definitions for Differential Output Signals .................................................................................... 81

Speed Bin Tables ............................................................................................................................................ 82

Electrical Characteristics and AC Operating Conditions ................................................................................... 86

Command and Address Setup, Hold, and Derating .......................................................................................... 104

Data Setup, Hold, and Derating ...................................................................................................................... 111

Commands – Truth Tables ............................................................................................................................. 120

Commands ................................................................................................................................................... 123

DESELECT ................................................................................................................................................ 123

NO OPERATION ........................................................................................................................................ 123

ZQ CALIBRATION LONG ........................................................................................................................... 123

ZQ CALIBRATION SHORT .......................................................................................................................... 123

ACTIVATE ................................................................................................................................................. 123

READ ........................................................................................................................................................ 123

WRITE ...................................................................................................................................................... 124

PRECHARGE ............................................................................................................................................. 125

REFRESH .................................................................................................................................................. 125

SELF REFRESH .......................................................................................................................................... 126

DLL Disable Mode ..................................................................................................................................... 127

Input Clock Frequency Change ...................................................................................................................... 131

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x4, x8, x16 DDR3L SDRAM

Description

Write Leveling ............................................................................................................................................... 133

Write Leveling Procedure ........................................................................................................................... 135

Write Leveling Mode Exit Procedure ........................................................................................................... 137

Initialization ................................................................................................................................................. 138

Voltage Initialization/Change ........................................................................................................................ 140

Voltage Switching ............................................................................................................................... 141

Mode Registers .............................................................................................................................................. 142

Mode Register 0 (MR0) ................................................................................................................................... 143

Burst Length ............................................................................................................................................. 143

Burst Type ................................................................................................................................................. 144

DLL RESET ................................................................................................................................................ 145

Write Recovery .......................................................................................................................................... 146

Precharge Power-Down (Precharge PD) ...................................................................................................... 146

CAS Latency (CL) ....................................................................................................................................... 146

Mode Register 1 (MR1) ................................................................................................................................... 148

DLL ENABLE/DISABLE .............................................................................................................................. 148

Output Drive Strength ............................................................................................................................... 149

OUTPUT ENABLE/DISABLE ...................................................................................................................... 149

TDQS ENABLE .......................................................................................................................................... 149

On-Die Termination (ODT) ........................................................................................................................ 150

WRITE LEVELING ..................................................................................................................................... 150

Posted CAS Additive Latency (AL) ............................................................................................................... 150

Mode Register 2 (MR2) ................................................................................................................................... 152

CAS WRITE Latency (CWL) ........................................................................................................................ 152

AUTO SELF REFRESH (ASR) ....................................................................................................................... 153

SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 153

SRT versus ASR .......................................................................................................................................... 154

Dynamic On-Die Termination (ODT) ......................................................................................................... 154

Mode Register 3 (MR3) ................................................................................................................................... 155

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 155

MPR Functional Description ...................................................................................................................... 156

MPR Address Definitions and Bursting Order .............................................................................................. 157

MPR Read Predefined Pattern .................................................................................................................... 162

MODE REGISTER SET (MRS) Command ........................................................................................................ 162

ZQ CALIBRATION Operation ......................................................................................................................... 163

ACTIVATE Operation ..................................................................................................................................... 164

READ Operation ............................................................................................................................................ 166

WRITE Operation .......................................................................................................................................... 177

DQ Input Timing ....................................................................................................................................... 185

PRECHARGE Operation ................................................................................................................................. 187

SELF REFRESH Operation .............................................................................................................................. 187

Extended Temperature Usage ........................................................................................................................ 189

Power-Down Mode ........................................................................................................................................ 190

RESET Operation ........................................................................................................................................... 198

On-Die Termination (ODT) ............................................................................................................................ 200

Functional Representation of ODT ............................................................................................................. 200

Nominal ODT ............................................................................................................................................ 200

Dynamic ODT ............................................................................................................................................... 202

Dynamic ODT Special Use Case ................................................................................................................. 202

Functional Description .............................................................................................................................. 202

Synchronous ODT Mode ................................................................................................................................ 208

ODT Latency and Posted ODT .................................................................................................................... 208

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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