PI7C8954
PCI Quad UART
Datasheet
Revision 3
October 2018
1545 Barber Lane Milpitas, CA 95035
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Internet: http://www.diodes.com
Document Number DS40303 Rev 3-2
PI7C8954
IMPORTANT NOTICE
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Copyright © 2016, Diodes Incorporated
www.diodes.com
PI7C8954
Document Number DS40303 Rev 3-2
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October 2018
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PI7C8954
REVISION HISTORY
Date
09/12/14
12/09/15
Revision Number
0.1
1.0
Description
Preliminary Datasheet
Updated Section 1 Feature
Updated Section 6.3 Configuration Registers
Updated Section 9 Electrical Specification
Updated Section 9 Electrical Specification
Updated Section 11 Ordering Information
Updated Section 4 Pin Assignment
Updated Section 11 Ordering Information
Updated Section 4 Pin Assignment
Updated Section 9 Electrical Specification
Revision numbering system changed to whole number
Updated Section 11 Ordering Information
Updated Section 1 Features
Added Figure 10-2 Part Marking
01/06/16
08/25/16
12/02/16
09/20/17
10/17/18
1.1
1.2
1.3
2
3
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Document Number DS40303 Rev 3-2
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PI7C8954
Table of Contents
1.
2.
3.
4.
5.
FEATURES ........................................................................................................................................... 8
APPLICATIONS .................................................................................................................................. 8
GENERAL DESCRIPTION ................................................................................................................ 9
PIN ASSIGNMENT............................................................................................................................. 11
FUNCTIONAL DESCRIPTION ........................................................................................................13
5.1. CONFIGURATION SPACE ..........................................................................................................13
5.1.1.
PCI Configuration Space.......................................................................................................13
5.1.2.
UART Configuration Space ...................................................................................................13
5.2. DEVICE OPERATION..................................................................................................................14
5.2.1.
Configuration Access .............................................................................................................14
5.2.2.
I/O Reads/Writes ....................................................................................................................14
5.2.3.
Memory Reads/Writes ............................................................................................................14
5.2.4.
Mode Selection ......................................................................................................................14
5.2.5.
450/550 Mode ........................................................................................................................14
5.2.6.
Enhanced 550 Mode ..............................................................................................................14
5.2.7.
Enhanced 950 Mode ..............................................................................................................15
5.2.8.
Transmit and Receive FIFOs .................................................................................................15
5.2.9.
Automated Flow Control .......................................................................................................16
5.2.10. Internal Loopback..................................................................................................................17
5.2.11. Crystal Oscillator ..................................................................................................................18
5.2.12. Baud Rate Generation ...........................................................................................................19
6.
PCI OPERATION ...............................................................................................................................20
6.1. SUPPORTED PCI TRANSACTION .............................................................................................20
6.2. REGISTER TYPES .......................................................................................................................20
6.3. CONFIGURATION REGISTERS .................................................................................................20
6.3.1.
VENDOR ID REGISTER – OFFSET 00h ..............................................................................21
6.3.2.
DEVICE ID REGISTER – OFFSET 00h ...............................................................................21
6.3.3.
COMMAND REGISTER – OFFSET 04h ...............................................................................21
6.3.4.
STATUS REGISTER – OFFSET 04h......................................................................................21
6.3.5.
REVISION ID REGISTER – OFFSET 08h ............................................................................22
6.3.6.
CLASS CODE REGISTER – OFFSET 08h ............................................................................22
6.3.7.
CACHE LINE REGISTER – OFFSET 0Ch ...........................................................................22
6.3.8.
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch .....................................................22
6.3.9.
HEADER TYPE REGISTER – OFFSET 0Ch ........................................................................22
6.3.10. BASE ADDRESS REGISTER 0 – OFFSET 10h .....................................................................23
6.3.11. BASE ADDRESS REGISTER 1 – OFFSET 14h .....................................................................23
6.3.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ............................................................23
6.3.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch........................................................................23
6.3.14. CAPABILITIES POINTER REGISTER – OFFSET 34h .........................................................23
6.3.15. INTERRUPT LINE REGISTER – OFFSET 3Ch ....................................................................23
6.3.16. INTERRUPT PIN REGISTER – OFFSET 3Ch ......................................................................23
6.3.17. EEPROM CONTROL REGISTER – OFFSET DCh...............................................................24
7.
UART REGISTER DESCRIPTION ..................................................................................................25
7.1. REGISTER TYPES .......................................................................................................................25
7.2. REGISTERS IN I/O MODE ..........................................................................................................25
7.2.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................26
PI7C8954
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7.2.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h ..............................................................27
7.2.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................27
7.2.4.
INTERRUPT STATUS REGISTER – OFFSET 02h ................................................................27
7.2.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................28
7.2.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................28
7.2.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................29
7.2.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................29
7.2.9.
MODEM STATUS REGISTER – OFFSET 06h ......................................................................30
7.2.10. SPECIAL FUNCTION REGISTER – OFFSET 07h ...............................................................31
7.2.11. DIVISOR LATCH LOW REGISTER – OFFSET 00h, LCR[7] = 1 ........................................31
7.2.12. DIVISOR LATCH HIGH REGISTER – OFFSET 01h, LCR[7] = 1 ......................................32
7.2.13. SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[7] = 1 .................................................32
7.3. REGISTERS IN MEMORY-MAPPING MODE ...........................................................................33
7.3.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................38
7.3.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h ..............................................................38
7.3.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................39
7.3.4.
INTERRUPT STATUS REGISTER – OFFSET 02h ................................................................39
7.3.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................39
7.3.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................40
7.3.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................40
7.3.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................41
7.3.9.
MODEM STATUS REGISTER – OFFSET 06h ......................................................................42
7.3.10. SPECIAL FUNCTION REGISTER – OFFSET 07h ...............................................................43
7.3.11. DIVISOR LATCH LOW REGISTER – OFFSET 08h .............................................................43
7.3.12. DIVISOR LATCH HIGH REGISTER – OFFSET 09h ...........................................................43
7.3.13. ENHANCED FUNCTION REGISTER – OFFSET 0Ah .........................................................44
7.3.14. XON SPECIAL CHARACTER 1 – OFFSET 0Bh ...................................................................45
7.3.15. XON SPECIAL CHARACTER 2 – OFFSET 0Ch ..................................................................45
7.3.16. XOFF SPECIAL CHARACTER 1 – OFFSET 0Dh ................................................................45
7.3.17. XOFF SPECIAL CHARACTER 2 – OFFSET 0Eh ................................................................45
7.3.18. ADVANCE CONTROL REGISTER – OFFSET 0Fh ..............................................................45
7.3.19. TRANSMIT INTERRUPT TRIGGER LEVEL – OFFSET 10h ...............................................46
7.3.20. RECEIVE INTERRUPT TRIGGER LEVEL – OFFSET 11h ..................................................46
7.3.21. FLOW CONTROL LOW TRIGGER LEVEL – OFFSET 12h .................................................46
7.3.22. FLOW CONTROL HIGH TRIGGER LEVEL – OFFSET 13h ...............................................46
7.3.23. CLOCK PRESCALE REGISTER – OFFSET 14h ..................................................................47
7.3.24. RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[6] = 0 ..........................................47
7.3.25. LINE STATUS REGISTER COUNTER – OFFSET 15h, SFR[6] = 1 ....................................47
7.3.26. TRANSMIT FIFO DATA COUNTER – OFFSET 16h, SFR[7] = 1 .......................................47
7.3.27. SAMPLE CLOCK REGISTER – OFFSET 16h, SFR[7] = 0 .................................................47
7.3.28. GLOBAL LINE STATUS REGISTER – OFFSET 17h ............................................................48
7.3.29. GLOBAL INTERRUPT ENABLE REGISTER – OFFSET 18h ..............................................48
7.3.30. GLOBAL INTERRUPT STATUS REGISTER – OFFSET 19h ................................................48
7.3.31. TX OVERRUN REGISTER – OFFSET 1Ah ...........................................................................48
7.3.32. RX OVERRUN REGISTER – OFFSET 1Bh ..........................................................................48
7.3.33. INTERRUPT STATUS REGISTER – OFFSET 1Ch ...............................................................49
7.3.34. RX FIFO COUNTER – OFFSET 1Dh ...................................................................................49
7.3.35. TX FIFO COUNTER – OFFSET 1Eh ....................................................................................49
7.3.36. FCR MIRROR REGISTER – OFFSET 1Fh ...........................................................................49
7.3.37. USER DEFINED TIMEOUT COUNTER REGISTER-1 – OFFSET 20h...............................50
7.3.38. USER DEFINED TIMEOUT COUNTER REGISTER-2 – OFFSET 21h...............................50
7.3.39. USER DEFINED TRIGGER LEVEL REGISTER – OFFSET 22h .........................................50
7.3.40. USER DEFINED REGISTER ENABLE – OFFSET 23h........................................................50
7.3.41. TX IDLE COUNTER REGISTER– OFFSET 24h ..................................................................50
PI7C8954
Document Number DS40303 Rev 3-2
Page 5 of 69
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October 2018
© Diodes Incorporated
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