MT46H128M16LFDD-48 WT:C datasheet, PDF

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MT46H128M16LFDD-48 WT:C: DescriptionDRAM Chip Mobile LPDDR SDRAM 2Gbit 128Mx16 1.8V 60-Pin VFBGA; File Size1MB，96 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT46H128M16LFDD-48 WT:C Overview

DRAM Chip Mobile LPDDR SDRAM 2Gbit 128Mx16 1.8V 60-Pin VFBGA

MT46H128M16LFDD-48 WT:C Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	LTB
HTS	8542.32.00.36
DRAM Type	Mobile LPDDR SDRAM
Chip Density (bit)	2G
Organization	128Mx16
Number of Internal Banks	4
Number of Words per Bank	32M
Number of Bits/Word (bit)	16
Data Bus Width (bit)	16
Maximum Clock Rate (MHz)	208
Maximum Access Time (ns)	6.5\|5
Address Bus Width (bit)	16
Interface Type	LVCMOS
Minimum Operating Supply Voltage (V)	1.7
Typical Operating Supply Voltage (V)	1.8
Maximum Operating Supply Voltage (V)	1.95
Operating Current (mA)	130
Minimum Operating Temperature (°C)	-25
Maximum Operating Temperature (°C)	85
Supplier Temperature Grade	Wireless
Number of I/O Lines (bit)	16
Supplier Package	VFBGA
Pin Count	60
Standard Package Name	BGA
Mounting	Surface Mount
Package Height	0.55(Min)
Package Length	9
Package Width	8
PCB changed	60
Lead Shape	Ball

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2Gb: x16, x32 Automotive LPDDR SDRAM

Features

Automotive LPDDR SDRAM

MT46H128M16LF – 32 Meg x 16 x 4 Banks

MT46H64M32LF – 16 Meg x 32 x 4 Banks

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh; 32ms for the automotive temperature

range

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-48

Clock Rate

208 MHz

Access Time

4.8ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 128 Meg x 16 (32 Meg x 16 x 4 banks)

– 64 Meg x 32 (16 Meg x 32 x 4 banks)

• Addressing

– JEDEC-standard

• Plastic "green" package

– 60-ball VFBGA (8mm x 9mm)

– 90-ball VFBGA (8mm x 13mm)

• Timing – cycle time

– 4.8ns @ CL = 3 (208 MHz)

• Special Options

– Automotive (package-level burn-in)

• Operating temperature range

– From –40˚C to +85˚C

– From –40˚C to +105˚C

• Design revision

Notes:

1. Contact factory for availability.

2. Self refresh supported up to 85 ºC.

Mark

128M16

64M32

-48

Table 2: Configuration Addressing – 2Gb

Architecture

Configuration

Refresh count

Row addressing

Column addressing

128 Meg x 16

32 Meg x 16 x 4 banks

16K A[13:0]

2K A11, A[9:0]

64 Meg x 32

16 Meg x 32 x 4 banks

16K A[13:0]

1K A[9:0]

PDF: 09005aef8541eee0

t89m_auto_lpddr.pdf - Rev. H 01/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

2Gb: x16, x32 Automotive LPDDR SDRAM

Features

Contents

General Description ......................................................................................................................................... 8

Functional Block Diagrams ............................................................................................................................... 9

Ball Assignments ............................................................................................................................................ 11

Ball Descriptions ............................................................................................................................................ 13

Package Block Diagrams ................................................................................................................................. 15

Package Dimensions ....................................................................................................................................... 16

Electrical Specifications .................................................................................................................................. 18

Electrical Specifications – I

Parameters ........................................................................................................ 21

Electrical Specifications – AC Operating Conditions ......................................................................................... 27

Output Drive Characteristics ........................................................................................................................... 31

Functional Description ................................................................................................................................... 34

Commands .................................................................................................................................................... 35

DESELECT ................................................................................................................................................. 36

NO OPERATION ......................................................................................................................................... 36

LOAD MODE REGISTER ............................................................................................................................. 36

ACTIVE ...................................................................................................................................................... 36

READ ......................................................................................................................................................... 37

WRITE ....................................................................................................................................................... 38

PRECHARGE .............................................................................................................................................. 39

BURST TERMINATE ................................................................................................................................... 40

AUTO REFRESH ......................................................................................................................................... 40

SELF REFRESH ........................................................................................................................................... 41

DEEP POWER-DOWN ................................................................................................................................. 41

Truth Tables ................................................................................................................................................... 42

State Diagram ................................................................................................................................................ 47

Initialization .................................................................................................................................................. 48

Standard Mode Register .................................................................................................................................. 51

Burst Length .............................................................................................................................................. 52

Burst Type .................................................................................................................................................. 52

CAS Latency ............................................................................................................................................... 53

Operating Mode ......................................................................................................................................... 54

Extended Mode Register ................................................................................................................................. 55

Temperature-Compensated Self Refresh ...................................................................................................... 55

Partial-Array Self Refresh ............................................................................................................................ 56

Output Drive Strength ................................................................................................................................ 56

Status Read Register ....................................................................................................................................... 57

Bank/Row Activation ...................................................................................................................................... 59

READ Operation ............................................................................................................................................. 60

WRITE Operation ........................................................................................................................................... 71

PRECHARGE Operation .................................................................................................................................. 83

Auto Precharge ............................................................................................................................................... 83

Concurrent Auto Precharge ......................................................................................................................... 83

AUTO REFRESH Operation ............................................................................................................................. 89

SELF REFRESH Operation ............................................................................................................................... 90

Power-Down .................................................................................................................................................. 92

Deep Power-Down ..................................................................................................................................... 93

Clock Change Frequency ................................................................................................................................ 95

Revision History ............................................................................................................................................. 96

Rev. H - 1/17 ............................................................................................................................................... 96

Rev. G - 2/15 ............................................................................................................................................... 96

PDF: 09005aef8541eee0

t89m_auto_lpddr.pdf - Rev. H 01/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x16, x32 Automotive LPDDR SDRAM

Features

List of Figures

Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2

Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9

Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12

Figure 6: Single Rank, Single Channel (1 Die) Package Block Diagram .............................................................. 15

Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: DD ............................................................................. 16

Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: BQ ............................................................................ 17

Figure 9: Typical Self Refresh Current vs. Temperature .................................................................................... 26

Figure 10: ACTIVE Command ........................................................................................................................ 37

Figure 11: READ Command ........................................................................................................................... 38

Figure 12: WRITE Command ......................................................................................................................... 39

Figure 13: PRECHARGE Command ................................................................................................................ 40

Figure 14: DEEP POWER-DOWN Command ................................................................................................... 41

Figure 15: Simplified State Diagram ............................................................................................................... 47

Figure 16: Initialize and Load Mode Registers ................................................................................................. 49

Figure 17: Alternate Initialization with CKE LOW ............................................................................................ 50

Figure 18: Standard Mode Register Definition ................................................................................................. 51

Figure 19: CAS Latency .................................................................................................................................. 54

Figure 20: Extended Mode Register ................................................................................................................ 55

Figure 21: Status Read Register Timing ........................................................................................................... 57

Figure 22: Status Register Definition .............................................................................................................. 58

Figure 23: READ Burst ................................................................................................................................... 61

Figure 24: Consecutive READ Bursts .............................................................................................................. 62

Figure 25: Nonconsecutive READ Bursts ........................................................................................................ 63

Figure 26: Random Read Accesses .................................................................................................................. 64

Figure 27: Terminating a READ Burst ............................................................................................................. 65

Figure 28: READ-to-WRITE ............................................................................................................................ 66

Figure 29: READ-to-PRECHARGE .................................................................................................................. 67

Figure 30: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 68

Figure 31: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 69

Figure 32: Data Output Timing –

AC and

DQSCK .......................................................................................... 70

Figure 33: Data Input Timing ......................................................................................................................... 72

Figure 34: Write – DM Operation .................................................................................................................... 73

Figure 35: WRITE Burst ................................................................................................................................. 74

Figure 36: Consecutive WRITE-to-WRITE ....................................................................................................... 75

Figure 37: Nonconsecutive WRITE-to-WRITE ................................................................................................. 75

Figure 38: Random WRITE Cycles .................................................................................................................. 76

Figure 39: WRITE-to-READ – Uninterrupting ................................................................................................. 77

Figure 40: WRITE-to-READ – Interrupting ...................................................................................................... 78

Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 79

Figure 42: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 80

Figure 43: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 81

Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 82

Figure 45: Bank Read – With Auto Precharge ................................................................................................... 85

Figure 46: Bank Read – Without Auto Precharge .............................................................................................. 86

Figure 47: Bank Write – With Auto Precharge .................................................................................................. 87

Figure 48: Bank Write – Without Auto Precharge ............................................................................................. 88

Figure 49: Auto Refresh Mode ........................................................................................................................ 89

Figure 50: Self Refresh Mode .......................................................................................................................... 91

PDF: 09005aef8541eee0

t89m_auto_lpddr.pdf - Rev. H 01/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT46H128M16LFDD-48 WT:C Related Products

	MT46H128M16LFDD-48 WT:C	MT46H128M16LFDD-48 WT:C TR
Description	DRAM Chip Mobile LPDDR SDRAM 2Gbit 128Mx16 1.8V 60-Pin VFBGA	DRAM Chip Mobile LPDDR SDRAM 2Gbit 128Mx16 1.8V 60-Pin VFBGA
EU restricts the use of certain hazardous substances	Compliant	Compliant
ECCN (US)	EAR99	EAR99
Part Status	LTB	LTB
DRAM Type	Mobile LPDDR SDRAM	Mobile LPDDR SDRAM
Chip Density (bit)	2G	2G
Organization	128Mx16	128Mx16
Number of Internal Banks	4	4
Number of Words per Bank	32M	32M
Number of Bits/Word (bit)	16	16
Data Bus Width (bit)	16	16
Maximum Clock Rate (MHz)	208	208
Maximum Access Time (ns)	6.5\|5	5\|6.5
Address Bus Width (bit)	16	16
Interface Type	LVCMOS	LVCMOS
Minimum Operating Supply Voltage (V)	1.7	1.7
Typical Operating Supply Voltage (V)	1.8	1.8
Maximum Operating Supply Voltage (V)	1.95	1.95
Operating Current (mA)	130	130
Minimum Operating Temperature (°C)	-25	-25
Maximum Operating Temperature (°C)	85	85
Supplier Temperature Grade	Wireless	Wireless
Number of I/O Lines (bit)	16	16
Supplier Package	VFBGA	VFBGA
Pin Count	60	60
Standard Package Name	BGA	BGA
Mounting	Surface Mount	Surface Mount
Package Height	0.55(Min)	0.55(Min)
Package Length	9	9
Package Width	8	8
PCB changed	60	60
Lead Shape	Ball	Ball

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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