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ISPLSI 2032A-150LJN44

Description
IC CPLD 32MC 5.5NS 44PLCC
Categorysemiconductor    Programmable logic devices   
File Size14MB,129 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Environmental Compliance
Download Datasheet Parametric View All

ISPLSI 2032A-150LJN44 Overview

IC CPLD 32MC 5.5NS 44PLCC

ISPLSI 2032A-150LJN44 Parametric

Parameter NameAttribute value
Programmable typeIn-system programmable
Delay time tpd(1) maximum5.5ns
Supply voltage - internal4.75 V ~ 5.25 V
Number of logic elements/blocks8
Number of macro cells32
Number of gates1000
Number of I/Os32
Operating temperature0°C ~ 70°C(TA)
Installation typesurface mount
Package/casing44-LCC (J-lead)
Supplier device packaging44-PLCC(16.58x16.58)
Package Diagrams
November 2017
Data Sheet
16-Ball WLCS Package Option 1: iCE40 LP
Dimensions in Millimeters
r
4 3 2 1
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
5
aaa
(4X)
e
D1
A
B
C
D
D
s
e
E1
TOP VIEW
BOTTOM VIEW
A
E
B
3
.16 X
Ø
b
Ø
.05
Ø
.015
M C A B
M C
A
ccc C
4
C
A
1
SIDE VIEW
REF.
A
A1
b
D
E
D1
E1
e
aaa
ccc
r
s
Min.
0.413
0.122
0.188
Nom.
Max.
0.452 0.491
0.182
0.152
0.248
0.218
1.40 BSC
1.48 BSC
1.05 BSC
1.05 BSC
0.35 BSC
0.03
0.03
0.175
0.215
NOTES:
1. ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3
DIMENSION “b” IS MEASURES AT THE MAXIMUM BUMP DIAMETER
PARALLEL TO PRIMARY DATUM C.
PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BUMPS.
BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE
PACKAGE BODY.
4
5
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
pkg_5.4

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