Integrated Power Semiconductors, Control IC & Passives
Features
•
•
•
•
•
•
•
•
•
•
3.3V to 12V input voltage1
20A maximum load capability, with no derating up to T
PCB
= 90°C
5 bit DAC settable, 0.925V to 2V output voltage range
2
Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit
3
200kHz or 300kHz nominal switching frequency
Optimized for very low power losses
Over & undervoltage protection
Adjustable lossless current limit
Internal features minimize layout sensitivity *
Very small outline 14mm x 14mm x 3mm
iP1001 Power Block
Description
The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.
The iP1001 is optimized for single-phase applications, and includes a full function fast transient response
PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark
power density. Very few external components are required, including output inductor, input & output capacitors.
Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and
operation up to 3.3Vout can be achieved with a simple external voltage divider.
iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers
benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,
heat transfer and component selection.
iP1001 Internal Block Diagram
V
IN
D0
D1
5 Bit
D2
DAC D3
D4
ENABLE
PGOOD
ILIM
FREQ
V
DD
PWM
& Driver
V
SW
SGND
GNDS
V
FS
V
F
PGND
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be
applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The
iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable
and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.
www.irf.com
05/20/03
1
iP1001
Parameter
V
IN
to PGND
V
DD
to PGND
V
FS
V
F
D0-D4
PGOOD to PGND
ENABLE to PGND
ILIM
FREQ
Output RMS Current
Block Temperature
All specifications @ 25°C (unless otherwise specified)
Absolute Maximum Ratings
Symbol
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
-40
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
16.0
6.0
V
DD
+0.3
V
DD
+0.3
V
DD
+0.3
6.0
6.0
V
DD
+0.3
V
DD
+0.3
20
125
Units
Conditions
V
T
BLK
A
°C
Recommended Operating Conditions
Parameter
Supply Voltage
Input Voltage Range
1
Output RMS Current from V
SW
4
Output Voltage Range
2
Symbol
V
DD
V
IN
Iout
VSW
V
OUT
Min
4.5
3.3
-
0.925
Typ
-
-
-
-
Max
5.5
12
20
2.0
Units
V
A
V
DAC Setting
see VID code, Table1.
Conditions
With 4.5V<V
DD
<5.5V
Electrical Specifications @ V
DD
= 5V & T
PCB
0°C - 90°C (Unless otherwise specified)
Parameter
Power Loss
Over Current Shutdown
Soft Start Time
Output Voltage Accuracy
V
F
Input Resistance
Frequency
V
DD
Undervoltage Lockout
Output Undervoltage Shutdown
Threshold
Output Undervoltage Protection
Blanking Time
Output Overvoltage Shutdown
Threshold at V
F
PGOOD Trip Threshold
PGOOD Leakage Current
PGOOD Output Low Voltage
Logic Input High Voltage
Logic Input Low Voltage
PGOOD
FREQ
Symbol
P
LOSS
Min
-
-
-
-2
-
-
-
-
-
-
-
-
-
-
2.4
-
Typ
3.1
25
1.8
-
181
200
300
4.2
0.8
20
2.25
V
DAC
-5%
1
-
-
-
Max
3.9
-
-
2
-
-
-
-
-
-
-
-
-
0.4
-
0.8
Units
W
A
ms
%
kΩ
kHz
V
V
ms
V
V
µA
V
V
V
ENABLE going high on start-up
See OVP note in Design
Guidelines
At V
F
PGOOD output high
Forced to 5.5V
I
sink
= 1mA
D0-D4, Enable
D0-D4, Enable
freq pin connected to V
DD
freq pin floating
200mV hysteresis
All DAC codes
T
BLK
= -40°C to 125°C
Conditions
300kHz, 12V
IN
, 1.3Vout, 20A
V
IN
=12V, V
OUT
=1.3V,
FREQ=300KHz, R
LIM
=340k
2
www.irf.com
iP1001
Electrical Specifications (continued)
Parameter
V
DD
Operating Current
V
DD
Quiescent Current
V
IN
Quiescent Current
ILIM to SGND Internal Resistance
Symbol
I
VDD
I
QVDD
I
QVIN
Min
-
-
-
-
Typ
25
600
-
300
Max
-
-
1
-
Units
mA
µA
mA
kΩ
Conditions
Enable High, 300kHz
Shutdown mode
Enable Low, VIN = 12V
Measured ILIM pin to SGND
Notes :
1
For Vin less than 4.5V requires external 5V
DD
supply.
2
Can be modified to operate up to 3.3V
OUT
, outside of DAC settable range. See Design Guidelines on how to set
3
4
output voltage greater than 2V.
See design guidelines.
See Fig. 5 for Recommended Operating Area
www.irf.com
3
iP1001
Guaranteed Performance Curves
5.0
4.5
4.0
Output Current (A)
V
IN
= 12V
V
OUT
= 1.3V
T
BLK
=125°C
f
sw
set to 300kHZ
Maximum
22
20
18
16
14
12
10
8
6
4
2
0
V
IN
= 12V
V
OUT
= 1.3V
f
sw
set to 300kHZ
Power Loss (W)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
Safe Operating Area
Typical
2
4
6
8
10
12
14
16
18
20
0
10
20
30
40
50
60
70
80
90 100 110 120 130
Output Current (A)
PCB Temperature (°C)
Fig 1.
Power Loss vs Current
Fig 2.
Safe Operating Area (SOA) vs T
PCB
Adjusting the Power Loss and SOA curves for different operating conditions
To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3,
or 4 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the
normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting
product is the final power loss based on all factors.
To make adjustments to the SOA curve in Fig. 2, determine the maximum allowed PCB temperature in Fig. 2 at the required
operating current. Then, add the correction temperature from the normalized curves in Figs. 3 or 4 to find the final maximum
allowable PCB temperature. When multiple adjustments are required, add all of the temperatures together, then add the sum
to the PCB temperature indicated on the SOA graph to determine the final maximum allowable PCB temperature based on
all factors.
Note: If input voltage <5Vin nominal operation is required then first see Fig. 5 for maximum current capability limit.
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