SH3002 MicroBuddy™
Reset Management and Clock Management
Support IC for Microcontrollers
SYSTEM MANAGEMENT
Description
The programmable SH3002 MicroBuddy™ (µBuddy™)
provides mandatory microcontroller support functions:
♦
CPU Supervisor
♦
Clock Management System
♦
Auxiliary functions
Three components make a complete system: any
microcontroller, the SH3002, and a bypass capacitor.
This low-cost system would consume very little power and
have clock-frequency accuracy of ± 0.5%.
The SH3002 can operate completely stand-alone, or
under control of the microcontroller. A single-wire
interface handles both bi-directional communications and
the interrupt / wake-up signal from the SH3002. The
SH3002 stores all configuration, calibration, parameters,
and status information in a 36-byte bank of control
registers. On reset, most of these are reloaded with
defaults from the factory-set nonvolatile memory. The
microcontroller can change any settings on the fly. If
some of the settings must remain fixed, a comprehensive
set of write-protect bits is provided for several related
groups of registers (with both permanent write-inhibit and
lock/unlock capabilities).
Features
♦
♦
Highly integrated IC
- 3 mm x 3 mm x 0.9 mm 16-lead MLP (QFN) package
CPU Supervisor
- Low V
DD
reset programmable from 2.3 V to 4.3 V
- Both active-high and active-low reset outputs
Clock Management System
- Replaces high-frequency (HF) crystal or resonator
- Programmable clock output from 32.768 kHz to 16 MHz
- Speed shift between multiple clock frequencies
- Adjustable spectrum spreading for EMI reduction
- Directly supports microcontroller STOP function
- Deep sleep with instantaneous auto-wakeup
Operates from 2.3 V to 5.5 V
- Ideal for battery-operated devices
I
DD
<850
µA
/ 2 MHz, <3 mA / 16 MHz, <10
µA
/ standby
♦
♦
♦
Pin Configuration
CLK
OUT
CLK
IN
15
Applications
♦
♦
♦
♦
♦
Home automation and security
Consumer products
Portable/handheld computers
Industrial equipment
Any microcontroller-based product
V
SS
V
REG
V
DD
NC
1
2
3
4
16
IO/I
NT
14
CLK32
13
12
11
µB
TM
SH3002
5
6
7
8
T
EST
(V
SS
)
RST
R
REF
10
N
RST
9
V+
C
BYPASS
V
DD
X
IN
X
OUT
GPIO
WITH
INT
16
15
14
13
N
RESET
3mm MLP (QFN) Package
1
2
3
4
µB
TM
SH3002
5
6
7
8
12
11
10
9
µController
G
ND
Covered by US Patent No. 6,903,986
Typical Application Circuit
Semtech, the Semtech logo, MicroBuddy, µBuddy, and µB are
marks of Semtech Corporation. All other marks belong to their
respective owners.
2005-08-08
Copyright ©2002-2005 Semtech Corporation 1
SH3002 data sheet V1.20
V
SS
V
SS
www.semtech.com
NC
NC
SH3002 MicroBuddy™
SYSTEM MANAGEMENT
Description
Ordering Information
SH3002IMLTR
EVK-SH3000USB
SH3000EK.pdf
SH3000UM.pdf
IC
SH3000 evaluation kit
SH3000 Evaluation Kit User Guide
SH3000 Reference Manual
MLP 3 x 3 mm, 16 pins, temp. range -40° C to +85° C
Block Diagram
Microcontroller
V
DD
32.768
K
H
Z
X
IN
X
OUT
R
ESET
I/O
PIN
V+
CLK
OUT
CLK32
2
3
13
16
CLK
IN
V
REG
V
DD
15
NC
4
Regulators
V
SS
Clock Driver &
Start/Stop Logic
Post-scaler
HF Oscillator
& FLL
Nonvolatile Memory
Calibration &
Default Settings
1
V
SS
8
NC
Voltage
Reference
LF Oscillator
RST
V
DD
Monitor
Reset Drivers
& Logic
11
N
RST
5
NC
10
Control Logic
T
EST
6
V
SS
12
7
R
REF
Periodic Interrupt
/ Wake-up Timer
RC
Oscillator
SH3002 µBuddy™
Interrupt
Serial I/O
IO/I
NT
9
14
Copyright ©2002-2005 Semtech Corporation
2
V1.20
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SH3002 MicroBuddy™
SYSTEM MANAGEMENT
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
Name
V
SS
V
REG
V
DD
NC
NC
NC
V
SS
V
SS
R
REF
N
RST
Type
Power
Power
Power
Function
Ground, 0 V. All V
SS
pins and T
EST
(V
SS
) pin must be connected together.
Output of internal Voltage Regulator, 2.2 V nominal. This pin can power external loads
of <5 mA. If load is “noisy” it requires a bypass capacitor. May be left unconnected or
used as a high logic level signal for CLK
SEL
pin (see below).
Main power supply, +2.3 to +5.5 V.
Not connected - reserved
Not connected - reserved
Not connected - reserved
Ground, 0 V. All V
SS
pins and T
EST
(V
SS
) pin must be connected together.
Ground, 0 V. All V
SS
pins and T
EST
(V
SS
) pin must be connected together.
Optional 1 MOhm external bias resistor for the internal 32.768 kHz RC oscillator. Can
be used to set, trim or modulate the internal RC oscillator. Keep open if not used.
Active low system reset output. Asserted with a strong low state when a reset condition
occurs. Weakly pulled to V
DD
internally when not active. This signal is valid for V
DD
as
low as 1 V. Keep open if not used.
Active high system reset output. Asserted with a strong high state when a reset
condition occurs. Weakly pulled to V
SS
internally when not active. This signal is valid
for V
DD
as low as 1 V. Keep open if not used.
Factory test enable. All V
SS
pins and T
EST
(V
SS
) pin must be connected together.
Buffered internal 32.768 kHz clock, derived according to the CLK
SEL
pin setting. This pin
uses backup power for the buffer when V
DD
is not present. When driving high, this signal
is either at V
BAK
or V
DD
(if V
DD
is higher than the reset threshold). When enabled, this
signal runs continuously independent of CLK
OUT
activity. Minimize the external load to
reduce power consumption during backup operations. When disabled, this pin is driven
to V
SS
. Keep open if not used.
Serial communications interface and interrupt output pin. This pin is internally weakly
pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is
programmed to be active low, this pin is weakly pulled to V
DD
when inactive. Keep
open if not used.
Clock activity sense input. Used to detect when the target microcontroller enters stop
mode (which disables its clock). Connect to the microcontroller’s clock output or
oscillator output pin. Connect to V
SS
when not used. CLK
IN
must not be left open.
Programmable high frequency clock output. Connect to the target microcontroller’s clock
input or oscillator input pin. Keep open if not used.
Power
Power
Analog
Digital Out
Digital Out
Digital In
RST
12 T
EST
(V
SS
)
13
CLK32
Digital Out
14
IO/I
NT
I/O
15
16
CLK
IN
CLK
OUT
Digital In
Digital Out
Copyright ©2002-2005 Semtech Corporation
3
V1.20
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SH3002 MicroBuddy™
SYSTEM MANAGEMENT
Functional Description
The SH3002 is a single-chip support system for
microcontrollers, microprocessors, DSPs and ASICs. It
consists of four major functional blocks, each block
having numerous enhancements over alternative
solutions.
The major modules are the CPU Supervisor, the
Clock Management System, and the Auxiliary functions.
The entire chip is controlled by the set of internal
registers and accessed via the single-pin serial interface.
All of the settings, configuration, and calibration or
operating parameters are programmable and re-
programmable at any time. All of the parameters
required for stand-alone operations are initialized on
reset from the built-in factory-programmed nonvolatile
memory. This allows the SH3002 to operate
autonomously for most of its supervisory functions. The
stand-alone operations do not require the use of the
serial interface or any of the initialization and control
operation, but without these, the full potential benefit of
the SH3002 might not be realized.
In the preferred configuration, where the SH3002 is
tightly coupled to the target micro, the SH3002 offers an
unprecedented level of design flexibility in clock and
power usage management.
The SH3002 is a particularly desirable integration
because the built-in features interact and meld to
produce more useful system level functions.
For example, on power up, the SH3002 can quickly
release the reset lines on its CPU Supervisor module
because the clock signal from the Clock Management
System is guaranteed to be running and stabilized. An
ordinary reset circuit must hold reset active for a long
time to allow an unknown crystal to start up and
stabilize.
The SH3002 offers several ways to minimize system
power consumption, such as allowing the target
processor to enter deep sleep by stopping its clock
completely, and to wake up as often as necessary with
no external support. The clock can be programmed to
start up at a given frequency, and software can adjust it
dynamically to manage power consumption and different
operating modes.
Users should consider the interactions of the major
functional blocks to gain the maximum advantage from
the SH3002.
The individual functional blocks are described in the
following sections.
Copyright ©2002-2005 Semtech Corporation
4
V1.20
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SH3002 MicroBuddy™
SYSTEM MANAGEMENT
CPU Supervisor
The SH3002 has two supervisory functions that
manage the reset of the target processor, a low V
DD
monitor (Brownout Detector), see
Figure 1.
Both functions are integrated with the Clock
Management System to provide a more complete
system solution than stand-alone components.
The SH3002 has both active high and active low
reset output pins. Both are driven strong to the active
state and weak to the inactive state. This eliminates the
need for external pull-ups and allows various reset
sources to be connected together in a wire-OR
configuration. (This makes it simple to set up a manual
reset circuit.)
A set of flags in the register map indicates the
source of the reset to the system software.
Low V
DD
Reset
The SH3002 drives the reset pins active whenever
V
DD
is below the value of V
BO
, the brownout reset
threshold, programmable from 2.3 V to 4.3 V in average
steps of 33 mV, see
Table 1.
Table 1.
Programmable V
BO
Values
Parameter
Min
Typ
VBO for min code
2.27
2.3
(000000)
VBO for max code
4.2
4.3
(111111)
Step resolution
33
Max
2.33
4.4
Units
V
V
mV
The default V
BO
value is loaded on power-up from the
factory-programmed nonvolatile memory. It can be re-
programmed at any time or it can be permanently
protected from any changes by setting the V
BO
Lock flag
or a write-protect flag.
On power up both the active-high and active-low
reset signals are driven active. These outputs are
typically valid for a V
DD
level of at least 0.5 V, and
guaranteed to be valid for a V
DD
level of 1.0 V.
The reset outputs remain active until V
DD
rises and
stays above the level of (V
BO
+ V
HYST
), where V
HYST
is
a small fixed amount of hysteresis, nominally 50 mV,
added to prevent nuisance reset activations (when V
DD
slowly changes near the level of V
BO
and some noise or
power glitching is present).
At the level of (V
BO
+ V
HYST
) the power supply is
considered valid. In case of the initial power-up, the
reset is then driven inactive once 6 ms of valid power
have elapsed. In the case of brownout, the reset is
released after a delay of 6 ms (but no less than 12 ms
from the beginning of the brownout).
Such a fast reset is possible because the SH3002
provides a fast-starting clock that is free of crystal start-
up time requirements. This gives the SH3002 an
advantage over most external reset circuits, which must
have a long reset pulse duration to accommodate long
and unpredictable crystal start-up times.
The SH3002 guarantees that a valid and stable
clock is available 2 ms before the reset signals are
negated, so that internal synchronous reset and
initialization of the target micro can proceed normally.
V
DD
Noise Filter
R
ESET
32.768kH
z
PWR
OK
1
Reset Logic
&
Minimum
Duration Timer
U
NDERFLOW
1→0
V
DD
20
K
RST
11
N
RST
20
K
Temperature- 4.40 V V
HIGH
compensated
Threshold
R
ESET
10
Voltage
Reference
Lock Logic
2.30 V
V
LOW
D/A
Hysteresis
50mV
TYP
.
Write-once
Initialization Logic
From / To
Serial I/O
6-bit Value
Figure 1.
CPU Supervisor --- Low V
DD
/ Brownout Detector, Watchdog, Reset logic & Drivers
Copyright ©2002-2005 Semtech Corporation
5
V1.20
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