LPC2361/2362
Single-chip 16-bit/32-bit MCU; up to 128 kB flash with ISP/IAP,
Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC
Rev. 5.1 — 15 October 2013
Product data sheet
1. General description
The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with up to 128 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical
performance in interrupt service routines and DSP algorithms, this increases performance
up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
The LPC2361/2362 are ideal for multi-purpose serial communication applications. They
incorporate a 10/100 Ethernet Media Access Controller (MAC) (LPC2362 only), USB full
speed device with 4 kB of endpoint RAM, four UARTs, two CAN channels, an SPI
interface, two Synchronous Serial Ports (SSP), three I
2
C interfaces, and an I
2
S interface.
This blend of serial communications interfaces combined with an on-chip 4 MHz internal
oscillator, SRAM of up to 32 kB, 16 kB SRAM for Ethernet (available as general purpose
SRAM for the LPC2361), 8 kB SRAM for USB and general purpose use, together with
2 kB battery powered SRAM make these devices very well suited for communication
gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit
DAC, one PWM unit, a CAN control unit, and up to 70 fast GPIO lines with up to 12 edge
or level sensitive external interrupt pins make these microcontrollers particularly suitable
for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz.
Up to 128 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
8 kB (LPC2361) or 32 kB (LPC2362) of SRAM on the ARM local bus for high
performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
8 kB SRAM for general purpose DMA use; also accessible by the USB.
Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA (LPC2362 only), USB DMA, and program execution from on-chip flash
with no contention between those functions. A bus bridge allows the Ethernet DMA to
access the other AHB subsystem.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I
2
S port, as well as for memory-to-memory transfers.
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
Serial interfaces:
Ethernet MAC with associated DMA controller (LPC2362 only). These functions
reside on an independent AHB.
USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels.
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA
controller.
Three I
2
C-bus interfaces (one with open-drain and two with standard port pins).
I
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
Other peripherals:
70 general purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 6 pins.
10-bit DAC.
Four general purpose timers/counters with a total of 8 capture inputs and 10
compare outputs. Each timer block has an external count input.
One PWM/timer block with support for three-phase motor control. The PWM has
two external count inputs.
Real-Time Clock (RTC) with separate power pin, clock source can be the RTC
oscillator or the APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt).
Two independent power domains allow fine tuning of power consumption based on
needed features.
Each peripheral has its own clock divider for further power saving.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip power-on reset.
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
LPC2361_62
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5.1 — 15 October 2013
2 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
3. Applications
Industrial control
Medical systems
Protocol converter
Communications
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC2361FBD100
LPC2362FBD100
LQFP100
LQFP100
Description
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
Version
SOT407-1
SOT407-1
Type number
4.1 Ordering options
Table 2.
Ordering options
Flash
(kB)
SRAM (kB)
Ethernet buffer
Ethernet
USB
device +
4 kB
FIFO
GP
DMA
Channels
CAN
ADC
DAC
Temp range
Type number
Local bus
GP/USB
Total
RTC
LPC2361FBD100
LPC2362FBD100
[1]
64
128
8
16
[1]
8
8
2
2
34 -
58 RMII
yes
yes
yes
yes
2
2
6
6
1
1
40 C
to +85
C
40 C
to +85
C
32 16
Available as general purpose SRAM for the LPC2361.
LPC2361_62
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5.1 — 15 October 2013
3 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
5. Block diagram
XTAL1
XTAL2
V
DDA
TMS TDI
trace signals
TRST
TCK TDO
EXTIN0
RESET
V
DD(3V3)
VREF
V
SSA
, V
SS
V
DD(DCDC)(3V3)
LPC2361/62
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
P0, P1, P2,
P3, P4
HIGH-SPEED
GPI/O
70 PINS
TOTAL
8/32 kB
SRAM
64/128 kB
FLASH
PLL
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
INTERNAL
CONTROLLERS
SRAM FLASH
ARM7TDMI-S
VECTORED
INTERRUPT
CONTROLLER
AHB
BRIDGE
8 kB
SRAM
AHB1
AHB2
AHB
BRIDGE
RMII(8)
ETHERNET
MAC WITH
DMA
(1)
16 kB
SRAM
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
AHB TO
APB BRIDGE
USB WITH
4 kB RAM
AND DMA
V
BUS
USB port 1
GP DMA
CONTROLLER
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
EINT3 to EINT0
P0, P2
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2,
2
×
MAT0/MAT1/
MAT3
6
×
PWM1
2
×
PCAP1
P0, P1
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
I
2
S INTERFACE
PWM1
SPI, SSP0 INTERFACE
LEGACY GPI/O
52 PINS TOTAL
SSP1 INTERFACE
6
×
AD0
A/D CONVERTER
UART0, UART2, UART3
AOUT
D/A CONVERTER
UART1
2 kB BATTERY RAM
VBAT
power domain 2
power domain 2
RTCX1
RTCX2
RTC
OSCILLATOR
REAL-
TIME
CLOCK
CAN1, CAN2
I
2
C0, I
2
C1, I
2
C2
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
WATCHDOG TIMER
SYSTEM CONTROL
002aad964
(1) LPC2362 only.
Fig 1.
LPC2361/2362 block diagram
LPC2361_62
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5.1 — 15 October 2013
4 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
6. Pinning information
6.1 Pinning
100
76
75
51
26
50
002aad965
1
LPC2361FBD100
LPC2362FBD100
25
Fig 2.
LPC2361/2362 pinning
6.2 Pin description
Table 3.
Symbol
P0[0] to P0[31]
Pin description
Pin
Type
I/O
Description
Port 0:
Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the pin
connect block. Pins 12, 13, 14, and 31 of this port are not available.
P0[0] —
General purpose digital input/output pin.
RD1 —
CAN1 receiver input.
TXD3 —
Transmitter output for UART3.
SDA1 —
I
2
C1 data input/output (this is not an open-drain pin).
P0[1] —
General purpose digital input/output pin.
TD1 —
CAN1 transmitter output.
RXD3 —
Receiver input for UART3.
SCL1 —
I
2
C1 clock input/output (this is not an open-drain pin).
P0[2] —
General purpose digital input/output pin.
TXD0 —
Transmitter output for UART0.
P0[3] —
General purpose digital input/output pin.
RXD0 —
Receiver input for UART0.
P0[4] —
General purpose digital input/output pin.
I2SRX_CLK —
Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the
I
2
S-bus specification.
RD2 —
CAN2 receiver input.
CAP2[0] —
Capture input for Timer 2, channel 0.
P0[0]/RD1/TXD3/
SDA1
46
[1]
I/O
I
O
I/O
P0[1]/TD1/RXD3/
SCL1
47
[1]
I/O
O
I
I/O
P0[2]/TXD0
P0[3]/RXD0
P0[4]/I2SRX_CLK/
RD2/CAP2[0]
98
[1]
99
[1]
81
[1]
I/O
O
I/O
I
I/O
I/O
I
I
LPC2361_62
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5.1 — 15 October 2013
5 of 65
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