Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
CC
= +2.7V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
CC
= +5V, T
A
= +25°C.) (Note 1)
PARAMETER
Operating Voltage Range
Supply Current
Debounce Duration
Input Threshold
Input Hysteresis
Input Pullup Resistance
IN Input Current
Input Voltage Range
Undervoltage-Lockout Threshold
OUT_,
CH
Output Voltage
EN
Pulse Width
EN
Threshold
EN
Input Current
EN
Low to Out Active
Propagation Delay
EN
High to Out Three-State
Propagation Delay
EN
Low to
CH
Out High
Propagation Delay
OUT_ Three-State Leakage Current
ESD CHARACTERISTICS
IEC 1000-4-2 Air-Gap Discharge
ESD Protection
IN_
IEC 1000-4-2 Contact Discharge
Human Body Model
±15
±8
±15
kV
I
IL
t
PE
t
PD
t
PC
V
OL
V
OH
t
EN
I
SINK
= 1.6mA
I
SOURCE
= 0.4mA
V
CC
= 5V
V
CC
- 1.0
200
0.8
0.8
1.7
1.1
2.4
2.0
±1
100
100
100
±10
I
IN
V
IN
V
IN
= ±15V
SYMBOL
V
CC
I
CC
t
DP
V
IL
V
IH
V
CC
= 5V
2.4
2.0
300
32
-25
1.9
63
100
±1
+25
2.6
0.4
V
CC
= 2.7V
MAX6818
CONDITIONS
V
CC
= 5V, I
OUT
= 0A, IN_ = V
CC
MAX6816/MAX6817
MIN
2.7
6
20
20
40
50
TYP
MAX
5.5
20
40
80
0.8
UNITS
V
µA
ms
V
V
mV
kW
mA
V
V
V
ns
V
µA
ns
ns
ns
µA
V
CC
= 2.7V
R
L
= 10kW, C
L
= 100pF
R
L
= 1kW, C
L
= 15pF
R
L
= 10kW, C
L
= 50pF
V
OUT
= 0V or V
CC
Note 1:
MAX6816 and MAX6817 production testing is done at T
A
= +25°C; overtemperature limits are guaranteed by design.
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Maxim Integrated
│
2
MAX6816/MAX6817/
MAX6818
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
±15kV ESD-Protected, Single/Dual/Octal,
CMOS Switch Debouncers
SUPPLY CURRENT vs. TEMPERATURE
MAX6816 toc01
7
6
SUPPLY CURRENT (µA)
5
4
3
2
1
0
V
CC
= 3V
V
CC
= 5V
DEBOUNCE OF CLOSING SWITCH
MAX6816 TOC02
DEBOUNCE OF OPENING SWITCH
MAX6816 TOC03
IN (5V/div)
IN (5V/div)
OUT (2V/div)
5V
5V
-5V
4V
-5V
4V
OUT (2V/div)
0V
V
CC
= 5V
10ms/div
0V
V
CC
= 5V
10ms/div
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (C)
OUTPUT LOGIC LEVEL
vs. SUPPLY VOLTAGE
MAX6816 toc04
MAX6818
EN
INPUT LOGIC THRESHOLD
vs. SUPPLY VOLTAGE
MAX6816 toc05
6
V
OH
, I
SOURCE
= 0.4mA
OUTPUT LOGIC LEVEL (V)
5
4
3
2
1
V
OL
, I
SINK
= 1.6mA
0
2
3
4
5
5
4
3
2
1
0
6
LOGIC THRESHOLD (V)
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DEBOUNCE DELAY PERIOD
vs. TEMPERATURE
MAX6816 toc06
V
CC
UNDERVOLTAGE LOCKOUT
vs. TEMPERATURE
V
CC
UNDERVOLTAGE LOCKOUT (V)
MAX6816 toc07
50
DEBOUNCE DELAY PERIOD (ms)
5
4
3
2
1
0
45
V
CC
= 5V
40
V
CC
= 3V
35
30
-40 -25 -10 5 20 35 50 65 80 95 100 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 100 125
TEMPERATURE (°C)
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Maxim Integrated
│
3
MAX6816/MAX6817/
MAX6818
Pin Description
PIN
MAX6816
1
2
—
—
3
—
—
4
—
—
MAX6817
2
—
1, 3
—
—
4, 6
—
5
—
—
MAX6818
10
—
—
2–9
—
—
12–19
20
1
11
NAME
GND
IN
IN1, IN2
IN1–IN8
OUT
OUT2, OUT1
OUT8–OUT1
V
CC
EN
CH
±15kV ESD-Protected, Single/Dual/Octal,
CMOS Switch Debouncers
FUNCTION
Ground
Switch Input
Switch Inputs
Switch Inputs
CMOS Debounced Output
CMOS Debounced Outputs
CMOS Debounced Outputs
+2.7V to +5.5V Supply Voltage
Active-Low, Three-State Enable Input for outputs. Resets
CH.
Tie to GND to “always enable” outputs.
Change-of-State Output. Goes low on switch input change of
state. Resets on
EN.
Leave unconnected if not used.
V
CC
V
CC
V
CC
R
PU
IN
ESD
PROTECTION
OSC.
D
R
COUNTER
Q
D
Q
OUT
LOAD
UNDER-
VOLTAGE
LOCKOUT
MAX6816
MAX6817
MAX6818
Figure 1. Block Diagram
Detailed Description
Theory of Operation
The MAX6816/MAX6817/MAX6818 are designed to
eliminate the extraneous level changes that result from
interfacing with mechanical switches (switch bounce).
Virtually all mechanical switches bounce upon opening or
closing. These switch debouncers remove bounce when
a switch opens or closes by requiring that sequentially
clocked inputs remain in the same state for a number of
sampling periods. The output does not change until the
input is stable for a duration of 40ms.
The circuit block diagram (Figure 1) shows the
functional blocks consisting of an on-chip oscillator, counter,
exclusive-NOR gate, and D flip-flop. When the input
does not equal the output, the XNOR gate issues a
counter reset. When the switch input state is stable for
the full qualification period, the counter clocks the flip-flop,
updating the output. Figure 2 shows the typical opening
and closing switch debounce operation. On the MAX6818,
the change output (CH) is updated simultaneously with the
switch outputs.
Undervoltage Lockout
The undervoltage-lockout circuitry ensures that the
out-puts are at the correct state on power-up. While
the supply voltage is below the undervoltage threshold
(typically 1.9V), the debounce circuitry remains
transparent. Switch states are present at the logic outputs
with no debouce delay.
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Maxim Integrated
│
4
MAX6816/MAX6817/
MAX6818
±15kV ESD-Protected, Single/Dual/Octal,
CMOS Switch Debouncers
t
DP
IN1
EN
1/2
V
CC
t
EN
1/2
V
CC
OUT1–OUT8
OUT1
OUT1–OUT8
IN2
CH
OUT2
t
PE
1/2
V
CC
OUT NORMALLY
LOW
t
PD
V
OL
+ 0.5V
V
OH
- 0.5V
t
PD
t
PE
1/2
V
CC
OUT NORMALLY
HIGH
t
PC
1/2
V
CC
Figure 4. MAX6818 μP Interface Timing Diagram
CH
+V
CC
+V
CC
MAX6818 ONLY
0.1µF
SW1
IN1
EN
CH
I/O
IRQ
Figure 2. Input Characteristics
µP
20V
IN
(20V/div)
0V
-20V
SW8
IN8
MAX6818
OUT1
OUT8
D0
D7
4V
OUT
(2V/div)
Figure 5. MAX6818 Typical μP Interfacing Circuit
0V
20ms/div
Figure 3. Switch Input ±25V Fault Tolerance
Robust Switch Inputs
inputs) to flow back into the V
CC
supply. If the total system
V
CC
supply current is less than the current flowing back
into the V
CC
supply, V
CC
will rise above normal levels.
In some low-current systems, a zener diode on V
CC
may
be required.
The switch inputs on the MAX6816–MAX6818 have
overvoltage-clamping diodes to protect against damaging
fault conditions. Switch input voltage scan safely swing
±25V to ground (Figure 3). Proprietary ESD-protection
structures protect against high ESD encountered in
harsh industrial environments, membrane keypads, and
portable applications. They are designed to withstand
±15kV per the IEC 1000-4-2 Air-Gap Discharge Test and
±8kV per the IEC 1000-4-2 Contact Discharge Test.
Since there are 63kW (typical) pullup resistors
connected to each input, driving an input to -25V draws
approximately 0.5mA (up to 4mA for eight inputs) from
the V
CC
supply. Driving an input to +25V will cause
approximately 0.32mA of current (up to 2.6mA for eight
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic dis-
charges encountered during handling and assembly. The
MAX6816–MAX6818 have extra protection against static
electricity. Maxim’s engineers have developed state-of-
the-art structures to protect against ESD of ±15kV at the
switch inputs without damage. The ESD structures with-
stand high ESD in all states: normal operation, shutdown,
and powered down. After an ESD event, the MAX6816–
MAX6818 keep working without latchup, whereas other
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