EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

DTS24Z21-41SE [V001]

Description
RECP ASSY
CategoryThe connector   
File Size856KB,17 Pages
ManufacturerTE Connectivity
Websitehttp://www.te.com
Download Datasheet Parametric View All

DTS24Z21-41SE [V001] Overview

RECP ASSY

DTS24Z21-41SE [V001] Parametric

Parameter NameAttribute value
Connector Systemline to panel, line to panel
Sealableyes
Connectors and terminals terminate toWires and cables
Housing size21
shieldyes
Connector typefemale end, female end
Housing typeLock nut female end
Number of Positions41
Number of power supply locations0
Number of signal positions41
Pre-installedno
Shell plating materialblack zinc nickel alloy
Shell materialAluminum 6061-T6
Insulation MaterialsHard dielectric/silica gel
Sealedno
Contact Current Rating (Max) (A)7.5
reverse polarityno
Terminal layout21 – 41
Terminal typesocket
Connector mounting typePanel
polar codeE
Joint alignment typekeying
joint fixationwith
Location monitoringTiming
Cable size.2 – .52 mm² [ 24 – 20 AWG ]
Working group temperature range-65 – 200 °C [ -85 – 392 °F ]
Circuit ApplicationSignal
Why can't we refresh two COM pins at the same time when there are multiple COM pins on the LCD screen?
Why can't we refresh two COM pins at the same time when there are multiple COM pins on the LCD screen?...
深圳小花 PCB Design
Question about alternating current
[size=14px]If the grid voltage is idealized as a standard sine wave[/size] [size=14px]its effective value is 220V, and its peak value is 311V[/size] [size=14px]But after all, it changes according to a...
shaorc Integrated technical exchanges
Realizing High-Performance Digital TV System Using FPGA
Digital television (DTV) has been adopted by most markets thanks to MPEG-2 compression technology, but the picture is not that simple. H.264-AVC (MPEG-4 Part 10) and Microsoft's VCI compression standa...
hzyhhw45 FPGA/CPLD
Why is my interrupt response time so long?
My clock cycle is 1/20uS, so my interrupt response time should be around 5/20uS, but the actual measured response time is around 2.5uS, which is much longer. I don't know what causes this? Can anyone ...
chenczy MCU
Classic Examples of Electronic Circuits
...
gauson Industrial Control Electronics
QuartusII compilation task problem
When I used QuartusII to simulate the I2C bus, I wrote a task task shift_in; output [7:0] shift; begin @(posedge scl) shift[7] = sda; @ (posedge scl) shift[6] = sda; @ (posedge scl) shift[5] = sda; @ ...
ulovefw FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2210  1240  1085  2423  1311  45  25  22  49  27 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号